DS567 Datasheet, PDF (12/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Design Implementation
Top-Level Design
The PPC440MC DDR2 Memory Controller is comprised of the controller, the physical layer, and the
FIFO interface as shown in Figure 3.
X-Ref Target - Figure 3
Physical Layer
DDR2 SDRAM
Controller
MC_TOP
MCI
Read/Write
FIFO
Clock, Reset,
I/O Control
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Figure 3: PPC440MC DDR2 Memory Controller Block Diagram
Physical Layer
The physical layer is comprised of the write datapath, the read datapath, the calibration state machine
for DQS and DQ calibration, the calibration logic for read enable alignment, and the memory
initialization state machine. The write datapath generates the data and strobe signals transmitted
during a Write command. The read datapath captures the read data in the read strobe domain.
Write Datapath
The write datapath, shown in Figure 4, is implemented using the IOB ODDR in the same edge mode.
Two data words are presented on the rising edge of the FPGA clock and the ODDR converts it into DDR
data.
X-Ref Target - Figure 4
Write Data Rise
D1
DQ
Write Data Fall
D2
FPGA Clock
Figure 4: Write Datapath
ODDR
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DS567 (v1.1.1) March 31, 2008