DS567 Datasheet, PDF (24/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Table 9: PPC440MC_DDR2 FPGA Performance and Resource Utilization for
XC5VFX100T-FF1136
Speed
Grade
f_MAX
(MHz)
C_DDR_
DWIDTH
Parameter Values
C_NUM_ C_INCLUDE_
RANKS_
ECC_
MEM SUPPORT
C_MIB_CM_
CLOCK_
RATIO
Slices
Device Resources
Block Slice 6-input
RAM Flip-Flops LUTs
-1
267
-2
300 16-bit
1
0
1:1
540
3
1105
1019
-3
333
-1
267
-2
300 32-bit
1
0
1:1
680
3
1415
1255
-3
333
-1
267
-2
300 64-bit
1
0
1:1
900
4
2025
1985
-3
333
-1
240
-2
270 72-bit
1
1
1:1
1527 6
2942
2230
-3
300
Revision History
Date
01/15/2008
03/19/2008
03/31/2008
Version
1.0
1.1
1.1.1
Revision
Initial Xilinx release with ISE™ 10.1 EDK software release.
Release with ISE 10.1 SP1 EDK software release.
Minor publication issue.
Notice of Disclaimer
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DS567 (v1.1.1) March 31, 2008