DS567 Datasheet, PDF (14/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Initialization
The initialization state machine (shown in Figure 6) powers up and initializes the DDR2 device and
performs the required reads and writes for the calibration. This state machine provides the required
delay and the command sequence required for the DDR2 device. After power up and initialization, the
state machine issues the read and write commands that are required for calibration. The state machine
asserts an initialization_done signal at the completion of the initialization and calibration. The
initialization state machine starts to execute after reset.
X-Ref Target - Figure 6
Idle
Wait 200 µs
Precharge 1
EMR2
Calib done
EMR3
Calib_read2
Enable DLL
Calib_write2
Reset DLL
Calib_read1
Precharge 2
Calib_write1
Auto-refresh 1
Activate
Auto-refresh 2
200 Cycle Wait
LM1
LM2
LM3
DS567_07_071607
Figure 6: Initialization State Machine Flow
Controller
The controller becomes active after the initialization state machine asserts the initialization_done
signal. The controller processes the commands from the MCI. The interface between the controller and
the MCI is explained in "Interfacing to the MCI."
FIFOs
The read and write datapaths have FIFOs for storing data. The FIFOs in Virtex-5 devices have a built-
in ECC module. For applications that require ECC, the ECC in the FIFOs can be used. The block RAMs
next to the PPC block are used to implement these FIFOs.
There is no latency impact during writes. The PPC440MC DDR2 Memory Controller operates with a
write data delay of zero, and the data is in the FIFO when it has to be sent to the memory. For reads,
there is a one-cycle latency hit because of using the FIFOs.
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DS567 (v1.1.1) March 31, 2008