DS567 Datasheet, PDF (20/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
In Figure 12, the internal_bank# waveforms are the internal bank registers. The internal_bank0 register
holds the most recently used bank and row, and the internal_bank3 register holds the least recently
used bank and row numbers. At clock 1, the PPC440MC DDR2 Memory Controller does not have any
banks open. In clock 2, the MCI presents a command for bank 0 and also asserts the conflict bit. The
PPC440MC DDR2 Memory Controller opens this bank and performs the write operation. Since no
banks are open, the PPC440MC DDR2 Memory Controller does not have to close a bank to open bank
0. The internal_bank0 register has bank 0, row 0 after the active command in clock 4. The MCI presents
a write command in clock 20 for bank 1. Because bank 1 has not been opened before, the PPC440MC
DDR2 Memory Controller opens bank 1 and performs the write operation. Only one bank, bank 0 was
kept open before this command. The PPC440MC DDR2 Memory Controller does not have to close any
banks to open bank 1. Bank 1 is now the most recently used bank, internal_bank0 now holds bank 1,
row 1, and internal_bank1 holds bank 0, row 0.
X-Ref Target - Figure 12
1 234
20
40
mi_mc_clk
MIMCBANKCONFLICT/
MIMCROWCONFLICT
MIMCADDRESSVALID
MIMCADDRESS
B0,R0
B1,R1
B3,R0
MIMCREADNOTWRITE
MCMIADDRREADYTOACCEPT
internal_auto_ref_flag
cmd_to_DDR2
internal_conflict
Act,B0
Wr,B0
Act,B1
Wr,B1
Act,B3
internal_bank0
B0,R0
B1,R1
B2,R0
internal_bank1
B0,R0
B1,R1
internal_bank2
B0,R0
internal_bank3
Figure 12: Bank Management with No Internal Banks Open
DS567_13_071607
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DS567 (v1.1.1) March 31, 2008