DS567 Datasheet, PDF (4/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
PPC440MC DDR2 Memory Controller Design Parameters
To create a uniquely tailored PPC440MC DDR2 Memory Controller, certain parameterizable features in
the PPC440MC DDR2 Memory Controller design allow a design that only utilizes the resources
required by the system and runs at the best possible performance. Table 2 lists the parameterizable
features in the PPC440MC DDR2 Memory Controller.
Table 2: PPC440MC DDR2 Memory Controller Design Parameters
Feature/Description
Parameter Name
Allowable Values
Default
Value
PPC440MC DDR2 Memory Controller Features
Target FPGA family
C_FAMILY
Base Address for Memory
C_MEM_BASEADDR
High Address for Memory
C_MEM_HIGHADDR
CPMINTERCONNECTCLK to
C_MIB_MC_CLOCK_RATIO 0 or 1 for 1:1, 2:1, or
0
PPC440MC DDR2 clock ratio
3:1clock ratios
2 for 3:2 clock ratio
DDR2 clock period (t_CK) in ps
MCI data width
C_MC_MIBCLK_PERIOD_PS 3000 to 8000
C_MIBDATA_WIDTH
128
3000
128
Number of generated clock pairs
C_NUM_CLK_PAIRS
1, 2, 4
1
supplied to the DDR2 memory
Supported number of external DDR2 C_NUM_RANKS_MEM
1, 2, 4
1
memory banks
Include ECC Logic
C_INCLUDE_ECC_SUPPORT 0 = Disable
0
1 = Enable
DDR2 Data Width
DDR2 Features
C_DDR_DWIDTH⁽¹⁾
16, 32, 64, 72
64
DDR2 Strobe Width
C_DDR_DQS_WIDTH
2, 4, 8, 9
8
DDR2 Data Mask Width
C_DDR_DM_WIDTH
2, 4, 8, 9
8
DDR2 Row Address Width
C_DDR_RAWIDTH
All supported memory row 14
address widths
DDR2 Column Address Width
C_DDR_CAWIDTH
All supported memory column 10
address widths
DDR2 Bank Address Width
C_DDR_BAWIDTH
2, 3
2
DDR2 CAS Latency
C_DDR_CAS_LAT⁽²⁾
3, 4, 5
5
DDR2 Burst Length
C_DDR_BURST_LENGTH⁽³⁾ 4, 8
4
DDR2 is a registered DIMM
C_REG_DIMM
0 = Unbuffered memory
1
1 = Registered memory
On Die Termination Selection
DDR2 ODT Width
C_DDR2_ODT_SETTING
C_DDR2_ODT_WIDTH
0 = Disables ODT
1
1 = ODT enabled, R_TT = 75Ω
2 = ODT enabled, R_TT = 150Ω
3 = ODT enabled, R_TT = 50Ω
0 to 4
1
DDR2 Additive Latency
C_DDR2_ADDT_LAT
0 to 4
0
Delay after ACTIVE command before C_DDR_TRCD
READ/WRITE command (ps)
15000
4
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DS567 (v1.1.1) March 31, 2008