DS567 Datasheet, PDF (5/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Table 2: PPC440MC DDR2 Memory Controller Design Parameters (Cont’d)
Feature/Description
Parameter Name
Allowable Values
Default
Value
Delay after ACTIVE command before C_DDR_TRAS
PRECHARGE command (ps)
40000
Delay after PRECHARGE command C_DDR_TRP
(ps)
15000
Delay after AUTOREFRESH before C_DDR_TRFC
another command (ps)
70000
Read to PRECHARGE command
delay (ps)
C_DDR_TRTP
7500
Write Recovery Time (ps)
C_DDR_TWR
15000
Write-to-Read Command Delay (ps) C_DDR_TWTR
10000
Average periodic refresh command C_DDR_TREFI
interval (ns)
7800
Skip 200 µs power up delay for
C_SIM_ONLY
0, 1
0
simulation
IDELAY high-performance mode
C_IDEL_HIGH_PERF
TRUE, FALSE
TRUE
log₂ of C_DQS_WIDTH
C_DQS_BITS
—
log₂ of C_DDR_DWIDTH
C_DQ_BITS
—
log₂ of C_NUM_RANKS_MEM
C_CS_BITS
—
0
Optional pipeline stage in read
C_READ_DATA_PIPELINE 0 or 1
0
data path
I/O column location of DQS groups C_DQS_IO_COL⁽⁴⁾⁽⁵⁾
See Table 3
Master/Slave location of DQ I/O
C_DQ_IO_MS⁽⁵⁾
See Table 3
Number of IDELAYCTRLs required C_NUM_IDELAYCTRL⁽⁶⁾
(log₂ of C_DQS_WIDTH)
1, 2, 3
Notes:
1. – MCI burst width of 32 for DDR2 data width of 16
– MCI burst width of 64 for DDR2 data width of 32
– MCI burst width of 128 for DDR2 data width of 64
2. When the parameter C_DDR_CAS_LAT is set to 3, the user must set the C_DDR2_ADDT_LAT parameter to any
value from 1 to 4.
3. – MCI burst length of 2 for DDR2 burst length of 4
– MCI burst length of 4 for DDR2 burst length of 8
4. C_DQS_IO_COL is always be 16'd0 because the PPC440MC interfaces use the left column banks.
5. If the optimal UCF provided in the pcore directory is not used and DQS and DQ bits are not placed in the banks
recommended in the optimal UCF then a PERL script (ftp://ftp.xilinx.com/pub/applications/misc/ar29313.zip) must
be used to determine the correct values of C_DQS_IO_COL and C_DQ_IO_MS. This script requires the user UCF
as its input. The PERL script outputs a UCF and a text file. The contents of the output UCF with additional
constraints for DQS and DQ must be appended to the user UCF. The text file with the correct values of
C_DQS_IO_COL and C_DQ_IO_MS must be copied to the .mhs file. The value for C_DQ_IO_MS depends on DQ
pin allocation.
6. The C_NUM_IDELAYCTRL parameter affects the number of instantiations of the IDELAYCTRL primitive in the RTL
code. This parameter value has to be set to 1, 2, or 3 depending on the number of FPGA banks used for DQS/DQ
signals. For example, if there are three FPGA banks being used to place DQS/DQ signals for a 64-bit memory
interface then this parameter C_NUM_IDELAYCTRL equals 3. The location constraints of the IDELAYCTRL
primitives have to be set in the UCF. The location coordinates for the IDELAYCTRL primitive depend on the FPGA
bank being used and can be determined using FPGA editor. The optimal UCFs provided in the pcore directory
already have the location constraints for the IDELAYCTRL primitives.
DS567 (v1.1.1) March 31, 2008
www.xilinx.com
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