DS567 Datasheet, PDF (18/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Change of Direction
The PPC440MC DDR2 Memory Controller deasserts MCMIADDRREADYTOACCEPT during
write_to_read or read_to_write to meet the DDR2 specification on change of direction. The duration of
the deassertion depends on the DDR2 specification. The MCI does not present any commands during
the deassertion of MCMIADDRREADYTOACCEPT in this case because it automatically holds off for
four clocks, and it also sees the MCMIADDRREADYTOACCEPT deassertion during the auto hold off
duration.
In Figure 10, the MCI presents a write command in clock 3 followed by a read command in clock 5. In
response to the read command in clock 5, the PPC440MC DDR2 Memory Controller deasserts
MCMIADDRREADYTOACCEPT and keeps it deasserted until the write_to_read turnaround time is
met. The write_to_read turnaround and read_to_write turnaround times depend on the memory vendor
specification. In clock 11 the MCI presents a write command. The PPC440MC DDR2 Memory
Controller does not deassert MCMIADDRREADYTOACCEPT because the read_to_write turnaround
time is two clocks. It is covered by the auto hold off of four clocks by the MCI.
X-Ref Target - Figure 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
mi_mc_clk
MIMCBANKCONFLICT/
MIMCROWCONFLICT
MIMCADDRESSVALID
MIMCADDRESS
B0,R0
B1,R1
B0,R0
MIMCREADNOTWRITE
MCMIADDRREADYTOACCEPT
internal_auto_ref_flag
cmd_to_DDR2
Wr,B0
Rd,B1
Wr,B0
Figure 10: Write Command Followed by Read Command
DS567_11_071607
Initialization
The MCMIADDRREADYTOACCEPT signal is deasserted during the entire duration of initialization and
calibration. At the end of the initialization and calibration sequence, the PPC440MC DDR2 Memory
Controller asserts the MCMIADDRREADYTOACCEPT signal. The calibration sequence is done once
during initialization and is not repeated.
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DS567 (v1.1.1) March 31, 2008