DS567 Datasheet, PDF (10/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
An address offset is calculated based on the width of the DDR2 data bus. The DDR2 column address
locations are calculated based on the offset, followed by the row address and bank address. Table 7
shows the bit locations for the DDR2 address bus. The address, which is from the MCI, is in big-Endian
format.
Table 7: Calculation of Address Bits
Variable
Equation
ADDR_OFFSET
COLADDR_STARTBIT
log₂(C_DDR_DWIDTH/8)
MCI_ADDR_WIDTH – (C_DDR_CAWIDTH+ADDR_OFFSET)
COLADDR_ENDBIT
COLADDR_STARTBIT + C_DDR_CAWIDTH – 1
ROWADDR_STARTBIT COLADDR_STARTBIT – C_DDR_AWIDTH
ROWADDR_ENDBIT
ROWADDR_STARTBIT + C_DDR_AWIDTH – 1
BANKADDR_STARTBIT ROWADDR_STARTBIT – C_DDR_BAWIDTH
BANKADDR_ENDBIT BANKADDR_STARTBIT + C_DDR_BAWIDTH – 1
Table 8 shows an example of the address mapping. In this example, the DDR2 data width is 32, the
column address width is 9, the row address width is 13, and the bank address width is 2.
Table 8: Example Address Mapping
(C_DDR_DWIDTH=32, C_DDR_CAWIDTH=9, C_DDR_RAWIDTH=13, C_DDR_BAWIDTH=2)
Variable
Equation
Value
ADDR_OFFSET
COLADDR_STARTBIT
log₂(C_DDR_DWIDTH/8)
log₂(32/8) = 2
MCI_ADDR_WIDTH – (C_DDR_CAWIDTH+ADDR_OFFSET) 32 – (9 + 2) = 21
COLADDR_ENDBIT
COLADDR_STARTBIT + C_DDR_CAWIDTH – 1
21 + (9 - 1) = 29
ROWADDR_STARTBIT COLADDR_STARTBIT – C_DDR_AWIDTH
21 – 13 = 8
ROWADDR_ENDBIT ROWADDR_STARTBIT + C_DDR_AWIDTH – 1
8 + 13 - 1 = 20
BANKADDR_STARTBIT ROWADDR_STARTBIT – C_DDR_BAWIDTH
8–2=6
BANKADDR_ENDBIT BANKADDR_STARTBIT + C_DDR_BAWIDTH – 1
6+2–1=7
Row Conflict and Bank Conflict Mask Settings
The MI_ROWCONFLICT_MASK and MI_BANKCONFLICT_MASK parameters, set by the user, enable
the PPC440 Memory Controller Interface (MCI) to detect row address and bank address conflicts
between the current and previous command addresses. MI_ROWCONFLICT_MASK and
MI_BANKCONFLICT_MASK parameters must be set based on the address offset width, the memory
device column address width, the memory device row address width, and the memory device bank
address width. The address offset width equals log₂ (C_DDR_DWIDTH/8).
Figure 2 shows the address fields of MIMCADDRESS [0:35], the corresponding 32-bit
MI_BANKCONFLICT_MASK, and 32-bit MI_ROWCONFLICT_MASK for a memory interface with the
following parameters.
• C_DDR_DWIDTH = 64
• Address Offset = log₂(64/8) = 3
• Column Address Width = 10
• Row Address Width = 14
• Bank Address Width = 3
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DS567 (v1.1.1) March 31, 2008