DS567 Datasheet, PDF (7/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Table 3: C_DQS_IO_COL and C_DQ_IO_MS Parameter Values for .mhs File
UCF Name
C_DQS_IO_COL
C_DQ_IO_MS
ddr2_72_fx30t_ff665_banks_15_11_13_17
0b000000000000000000 0b1010110101010110101010101010101011
010101010110101010101011010101010110
10
ddr2_72_fx70t_ff665_banks_15_11_13_17
0b000000000000000000 0b1010110101010110101010101010101011
010101010110101010101011010101010110
10
ddr2_72_fx70t_ff1136_banks_15_11_13_17
0b000000000000000000 0b1011010101010110101010101010101010
101011010101010101010111010101101010
10
ddr2_72_fx100t_ff1136_banks_13_17_21_25 0b000000000000000000 0b1010110101010110101010101010101011
010101010110101010101011010101010110
10
ddr2_72_fx100t_ff1136_banks_23_19_15_11 0b000000000000000000 0b1010110101010110101010101010101011
010101010110101010101011010101010110
10
ddr2_72_fx100t_ff11738_banks_13_17_21_25 0b000000000000000000 0b1010110101010110101010101010101011
010101010110101010101011010101010110
10
ddr2_72_fx100t_ff11738_banks_23_19_15_11 0b000000000000000000 0b1010110101010110101010101010101011
010101010110101010101011010101010110
10
ddr2_72_fx130t_ff11738_banks_13_17_21_25 0b000000000000000000 0b1010110101010110101010101010101011
010101010110101010101011010101010110
10
ddr2_72_fx130t_ff11738_banks_23_19_15_11 0b000000000000000000 0b1010110101010110101010101010101011
010101010110101010101011010101010110
10
ddr2_72_fx200t_ff11738_banks_13_17_21_25 0b000000000000000000 0b1010110101010110101010101010101011
010101010110101010101011010101010110
10
ddr2_72_fx200t_ff11738_banks_23_19_15_11 0b000000000000000000 0b1010110101010110101010101010101011
010101010110101010101011010101010110
10
Allowable Parameter Combinations
The PPC440MC DDR2 Memory Controller allows up to four external ranks of memory. Individual rank
address ranges are calculated by C_MEM_BASEADDR and C_MEM_HIGHADDR. The ranges must
comprise a complete, contiguous power of two range such that range = 2^m, and the m least-significant
bits of C_MEM_BASEADDR must be zero.
All external memory ranges are calculated contiguous to each other in the system addressable space.
In addition, all external memory ranks are identical in size to other ranks of memory space.
The following is an example of an acceptable setting for four external ranks (for example, separate
DIMMs) of addressable memory, each equal in size to 256 MB. All addressable memory spaces are
accessible by all port modules.
C_NUM_MEM_RANKS = 4
C_MEM_BASEADDR=0x0000_0000
C_MEM_HIGHADDR=0x3FFF_FFFF
Equates to:
Memory Rank 0 Base Address = 0x0000_0000
Memory Rank 0 High Address = 0x0FFF_FFFF
Memory Rank 1 Base Address = 0x1000_0000
Memory Rank 1 High Address = 0x1FFF_FFFF
Memory Rank 2 Base Address = 0x2000_0000
Memory Rank 2 High Address = 0x2FFF_FFFF
Memory Rank 3 Base Address = 0x3000_0000
Memory Rank 3 High Address = 0x3FFF_FFFF
DS567 (v1.1.1) March 31, 2008
www.xilinx.com
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