DS567 Datasheet, PDF (15/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Clocking and Reset
The clocks and the reset signal are provided by the MCI. The MCI provides MI_MCCLK (at interface
frequency), MI_MCCLK90 (at interface frequency), MI_MCCLK_200 (200 MHz), and MI_MCRST
synchronized to MI_MCCLK. The PPC440MC DDR2 Memory Controller requires all four phases of the
clock. The CLK180 and CLK270 signals are generated by local inversion using MI_MCCLK and
MI_MCCLK90. The MI_MCRST from the MCI module is synchronized to CLK180, CLK270,
MI_MCCLK90, and the MI_MCCLK_200 before being used in the design.
Interfacing to the MCI
Handshaking between the PPC440MC DDR2 Memory Controller and the MCI is done with the
MCMIADDRREADYTOACCEPT signal. The following subsections describe this signal and its operation
under various conditions.
MCMIADDRREADYTOACCEPT
The PPC440MC DDR2 Memory Controller asserts the MCMIADDRREADYTOACCEPT signal when it
is ready to accept transactions from the MCI. The PPC440MC DDR2 Memory Controller completes all
transactions that it had accepted from the MCI. The MCI does not re-request a transaction; the
PPC440MC DDR2 Memory Controller has to complete all the transactions it accepted. The PPC440MC
DDR2 Memory Controller deasserts MCMIADDRREADYTOACCEPT during:
• Auto refresh
• Bank and row conflicts
• Change of direction (write to read and read to write)
• Initialization
Auto Refresh
The PPC440MC DDR2 Memory Controller deasserts the MCMIADDRREADYTOACCEPT signal once
the auto refresh flag is asserted internally. The auto refresh flag is asserted by the PPC440MC DDR2
Memory Controller when it has to perform an auto refresh function to the DDR2 memory. Due to the
synchronization delay, the MCI sees the deassertion of this signal after a delay of two clock cycles. The
MCI can request transactions when the PPC440MC DDR2 Memory Controller deasserts the
MCMIADDRREADYTOACCEPT signal because of the synchronization delay. The PPC440MC DDR2
Memory Controller asserts and deasserts this signal two cycles earlier to account for the
synchronization delay.
The minimum DDR2 burst size is four. When the PPC440MC DDR2 Memory Controller is set to a burst
of 4x64, the MCI must be set to a burst of 2x128. When set to the DDR2 burst size of four, the MCI can
request transactions every other clock, which can cause the MCI to request at least one transaction
while MCMIADDRREADYTOACCEPT is deasserted. The PPC440MC DDR2 Memory Controller
accepts requests from the MCI for up to two clocks after the deassertion of the
MCMIADDRREADYTOACCEPT signal. The transaction that was accepted by the PPC440MC DDR2
Memory Controller after the deassertion of the MCMIADDRREADYTOACCEPT signal is processed
after the auto refresh command completes.
DS567 (v1.1.1) March 31, 2008
www.xilinx.com
15