DS567 Datasheet, PDF (17/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Bank and Row Conflicts
During conflicts, the PPC440MC DDR2 Memory Controller deasserts the
MCMIADDRREADYTOACCEPT signal to service the conflict. The MCI asserts the conflict signal if the
bank or the row in the current access is different from the bank or the row in the previous access. The
MCI does not know of all the banks that are kept open in the PPC440MC DDR2 Memory Controller. It
keeps track of banks and rows from the current and previous accesses. Because the MCI does not keep
track of the history of banks and rows that were opened, the conflict signal asserted by the MCI during
some of the access might not be for real conflicts. The PPC440MC DDR2 Memory Controller evaluates
the conflict signal from the MCI and determines if the conflict is real or not. During real conflicts, the
PPC440MC DDR2 Memory Controller deasserts the MCMIADDRREADYTOACCEPT signal. During
fake conflicts, the PPC440MC DDR2 Memory Controller does not deassert
MCMIADDRREADYTOACCEPT. When MI_CONTROL:AUTOHOLD is set to 2’b10, the MCI holds off
for four PPC440MC DDR2 Memory Controller clocks whenever it asserts the conflict signal.
In Figure 9, the row and bank conflicts are ORed together and treated as one conflict. The MCI presents
three write commands to the PPC440MC DDR2 Memory Controller. The first write is to bank 0, row 0
(clock 3), the second write is to bank 1, row 1 (clock 5), and the third write is to bank 0, row 0 (clock
n+1). The PPC440MC DDR2 Memory Controller already opened bank 0 and row 0 in the previous
command (not shown in the figure). The MCI does not assert the conflict for the first write (clock 3)
because the bank and row are the same as the bank and row in the previous access.
X-Ref Target - Figure 9
1 2 3 4 5 6 7 8 9 10 n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8
mi_mc_clk
MIMCBANKCONFLICT/
MIMCROWCONFLICT
MIMCADDRESSVALID
MIMCADDRESS
B0,R0
B1,R1
B0,R0
MIMCREADNOTWRITE
MCMIADDRREADYTOACCEPT
internal_auto_ref_flag
cmd_to_DDR2
Wr,B0
Act,B1
Wr,B1
Wr,B0
Figure 9: Read Command with Conflict
ds567_10_031308
The MCI asserts the conflict bit while presenting the second write (clock 5). The conflict bit is asserted
because the row and bank are different from the row and bank in write 1 (clock 3). The PPC440MC
DDR2 Memory Controller had not opened bank 1, row 1 during any of its previous accesses. The
PPC440MC DDR2 Memory Controller evaluates this conflict as a real conflict and deasserts the
MCMIADDRREADYTOACCEPT signal in clock 7. The PPC440MC DDR2 Memory Controller opens
bank 1, row 1 and issues the write command. The PPC440MC DDR2 Memory Controller asserts the
MCMIADDRREADYTOACCEPT signal in clock 9 after it is ready to accept new requests.
When presenting the third write in clock n+1, the MCI asserts the conflict bit. It asserts the conflict bit
because the bank and row in the third write (clock n+1) is different from the bank and row in the second
write (clock 7). The PPC440MC DDR2 Memory Controller does not treat the third write (clock n+1) as
a conflict because the bank and row for the third write were opened during the first write and have not
been closed. The PPC440MC DDR2 Memory Controller evaluates this conflict as a fake conflict and
does not deassert the MCMIADDRREADYTOACCEPT signal. The PPC440MC DDR2 Memory
Controller takes one clock to evaluate the conflict, and there are at least four idle cycles in the
DDR2_data_bus.
DS567 (v1.1.1) March 31, 2008
www.xilinx.com
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