DS567 Datasheet, PDF (16/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
In Figure 7 through Figure 14, the DDR2 burst size is 4.
In Figure 7, the PPC440MC DDR2 Memory Controller deasserts the MCMIADDRREADYTOACCEPT
signal in clock 6 in response to the assertion of the internal auto refresh flag in clock 5. The MCI
presents two commands in clock 3 and clock 5, while the MCMIADDRREADYTOACCEPT signal is
asserted. The PPC440MC DDR2 Memory Controller processes both commands before the auto
refresh command to the memory. The PPC440MC DDR2 Memory Controller asserts the
MCMIADDRREADYTOACCEPT signal in clock 15 after the auto refresh command completes.
X-Ref Target - Figure 7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
mi_mc_clk
MIMCBANKCONFLICT/
MIMCROWCONFLICT
MIMCADDRESSVALID
MIMCADDRESS
A0
A1
MIMCREADNOTWRITE
MCMIADDRREADYTOACCEPT
internal_auto_ref_flag
cmd_to_DDR2
DDR2_data_bus
Wr,A0
Wr,A1
auto_ref
A0,D0 A0,D2 A1,D0 A1,D2
A0,D1 A0,D3 A1,D1 A1,D3
DS567_08_071607
Figure 7: Write Command During Auto Refresh and MCMIADDRREADYTOACCEPT Asserted
In Figure 8, the MCI presents a command in clock 7 after the deassertion of the
MCMIADDRREADYTOACCEPT signal. The PPC440MC DDR2 Memory Controller processes this
command after the auto refresh command completes. The assertion of the
MCMIADDRREADYTOACCEPT signal is delayed until the second write command completes. This can
be done because the MCI sees the assertion of the MCMIADDRREADYTOACCEPT signal late due to
the synchronization delay and has a minimum delay of two PPC440MC DDR2 Memory Controller
clocks before presenting a transaction.
X-Ref Target - Figure 8
12345678
mi_mc_clk
MIMCBANKCONFLICT/
MIMCROWCONFLICT
MIMCADDRESSVALID
MIMCADDRESS
A0
A1
MIMCREADNOTWRITE
MCMIADDRREADYTOACCEPT
internal_auto_ref_flag
cmd_to_DDR2
Wr,A0
Auto,ref
Wr,A1
DS567_09_071607
Figure 8: Write Command During Auto Refresh and MCMIADDRREADYTOACCEPT Deasserted
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DS567 (v1.1.1) March 31, 2008