DS567 Datasheet, PDF (1/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DS567 (v1.1.1) March 31, 2008
DDR2 Memory Controller for
PowerPC 440 Processors
Introduction
This data sheet describes the DDR2 Memory Controller
reference design for the PowerPC^® 440 block
embedded in the Virtex™-5 FXT Platform FPGAs. It
interfaces with the Memory Controller Interface (MCI)
and provides the control interface for DDR2 memory.
Features
• Supports a maximum performance of 333 MHz in
the fastest speed grade
• Supports 16-bit, 32-bit, and 64-bit data widths, and
72-bit data width with ECC (DQ:DQS = 8:1)
• Supports DDR2 SDRAM single-rank registered
DIMMs and components
• Supports the following DDR2 SDRAM features:
♦ CAS latencies (3, 4, 5)
♦ Additive latencies (0, 1, 2, 3, 4)
♦ On-die termination (ODT)
♦ Burst lengths (4, 8)
• Supports bank management (up to four banks
open)
• Performs the memory device initialization
sequence upon power-up
• Performs auto-refresh cycles
Reference Design Facts
Reference Design Specifics
Supported Device
Family
Virtex-5 FXT Platform FPGAs
Version of Reference
Design
PPC440MC
v1_01_a
Resources Used
LUTs
See Table 9
FFs
See Table 9
Block RAMs
See Table 9
Special Features
None
Provided with Reference Design
Documentation
Product Specification
Design File Formats Verilog
Constraints File
UCF – in EDK PCORE directory
Verification
Verilog Testbench
Instantiation Template Verilog Wrapper
Design Tool Requirements
Xilinx Implementation
Tools
ISE™ 10.1 SP1 or later
Verification
ModelSim SE/EE 6.0c or later
Simulation
ModelSim SE/EE 6.0c or later
Synthesis
XST
Support
See "Notice of Disclaimer."
© 2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of
IBM Corp. and used under license. All other trademarks are the property of their respective owners.
DS567 (v1.1.1) March 31, 2008
www.xilinx.com
1