DS567 Datasheet, PDF (11/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
X-Ref Target - Figure 2
0
...
56789
...
2223
...
3233 3435
Unused bits 3-bit
Bank Address
14-bit
Row Address
10-bit
3-bit
Column Address Address Offset
0
56789
31
0 ... 0 1 1 1 0
...
0
MI_BANKCONFLICT_MASK = 32’h03800000
0
0
...
89
22 23
0111111111111110
31
... ₀
MI_ROWCONFLICT_MASK = 32’h007FFE00
ds567_02_072307
Figure 2: MIMCADDRESS Bus and Corresponding MI_ROWCONFLICT_MASK and
MI_BANKCONFLICT_MASK
MI_ROWCONFLICT_MASK [0:31] corresponds to MIMCADDRESS [0:31] with the Row Address bits
set to ones and all other bits set to zeros to enable conflict detection. And the
MI_BANKCONFLICT_MASK [0:31] corresponds to MIMCADDRESS [0:31] with the Bank Address bits
set to ones and all other bits set to zeros to enable conflict detection.
Another example with reduced data width:
• C_DDR_DWIDTH = 32
• Address Offset = log₂(32/8) = 2
• Column Address Width = 10
• Row Address Width = 14
• Bank Address Width = 3
The MI_ROWCONFLICT_MASK and MI_BANKCONFLICT_MASK parameters are:
• MI_ROWCONFLICT_MASK = 32'h003fff00
• MI_BANKCONFLICT_MASK = 32'h01c00000
DS567 (v1.1.1) March 31, 2008
www.xilinx.com
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