DS567 Datasheet, PDF (2/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
Functional Description
The PPC440MC DDR2 Memory Controller interfaces directly to the PowerPC processor through the
MCI (see Figure 1). To achieve hardware functionality and maximum performance with the memory
controller interface, users should use the relevant optimal UCF provided in the EDK PCORE directory.
There is only one optimal UCF for each device/package/processor combination.
X-Ref Target - Figure 1
Virtex-5 Embedded Processor Block
DMA
DMA
LocalLink0
LocalLink1
FCM
Interface
Control
Interface
APU
Control
CPM/
Control
PowerPC 440
Processor
ICURD
DCURD
DCUWR
SPLB0
Memory
PPC440MC
MCI
Controller
DDR Memory
Interface
Controller
MPLB
SPLB1
DCR
DMA
LocalLink2
DMA
LocalLink3
DCR
Interface
ds567_01_030608
Figure 1: PPC440 MCI and PPC440MC DDR2 Memory Controller Block Diagram
I/O Signals
Table 1 defines the PPC440MC DDR2 Memory Controller signals.
Table 1: PPC440MC DDR2 Memory Controller I/O Signal Description
Signal Name
Interface
Signal
Type
Initial
Status
Description
PPC440 MCI Signals
MIMCREADNOTWRITE
MCI
I
This signal indicates if the operation is a
read or a write
MIMCADDRESS[0:35]
MCI
I
Address bus
MIMCADDRESSVALID
MCI
I
When asserted, this signal indicates the
data on the address bus is valid
MIMCWRITEDATA[0:127]
MCI
I
Data bus
MIMCBYTEENABLE[0:15]
MCI
I
Byte enable for the data on the data bus
MIMCWRITEDATAVALID
MCI
I
When asserted, this signal indicates the
data on the data bus is valid
MIMCBANKCONFLICT
MCI
I
This signal is asserted if the bank being
accessed is different from the bank
accessed in the previous command
2
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DS567 (v1.1.1) March 31, 2008