DS567 Datasheet, PDF (21/24 Pages) Xilinx, Inc – This data sheet describes the DDR2 Memory Controller

DDR2 Memory Controller for PowerPC 440 Processors
In Figure 13, the PPC440MC DDR2 Memory Controller has four banks open in clock 1. The MCI
presents a command for bank 0 in clock 2 and asserts the conflict bit. Bank 0 has already been opened
by the PPC440MC DDR2 Memory Controller. The conflict is a fake conflict. The PPC440MC DDR2
Memory Controller does not deassert the MCMIADDRREADYTOACCEPT signal. Internal_bank0 now
holds bank 0, indicating it is the most recently used bank. The commands presented in clocks 8, 15, and
22 are also fake conflicts. In clock 29, the MCI presents a command for bank 7. Bank 7 has not been
opened by the PPC440MC DDR2 Memory Controller, the conflict is a real conflict. The PPC440MC
DDR2 Memory Controller closes the least recently used bank (bank 0, which is held in internal_bank3)
and opens bank 7. The PPC440MC DDR2 Memory Controller also deasserts the
MCMIADDRREADYTOACCEPT signal to service the conflict.
X-Ref Target - Figure 13
12
8
15
22
29
mi_mc_clk
MIMCBANKCONFLICT/
MIMCROWCONFLICT
MIMCADDRESSVALID
MIMCADDRESS
B0,R0
B1,R1
B3,R0
B4,R1
B7,R1
MIMCREADNOTWRITE
MCMIADDRREADYTOACCEPT
internal_auto_ref_flag
cmd_to_DDR2
internal_conflict
Wr,B0
Wr,B1
Wr,B3
Wr,B4
Pre,B0 Act,B7
internal_bank0
B4,R1
B0,R0
B1,R1
B3,R0
B4,R1
B7, R1
internal_bank1
B1,R1
B4,R1
B0,R0
B1,R1
B3,R0
B4, R1
internal_bank2
B0,R0
B1,R1
B4,R1
B0,R0
B1,R1
B3, R0
internal_bank3
B3,R0
B3,R0
B3,R0
B4,R1
B0,R0
B1, R1
Figure 13: Bank Management with Four Internal Banks Open
DS567_14_071607
DS567 (v1.1.1) March 31, 2008
www.xilinx.com
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