XC4000FM Datasheet, PDF (7/40 Pages) Xilinx, Inc – Flexible function generators

inputs could not be driven by all adjacent routing lines. In
the XC4000 families, these constraints have been largely
eliminated. This makes it easier for the software to com-
plete the routing of complex interconnect patterns.
Chip architects and software designers worked closely
together to achieve a solution that is not only inherently
powerful, but also easy to utilize by the software-driven
design tools for Partitioning, Placement and Routing. The
goal was to provide automated push-button software tools
that complete almost all designs, even large and dense
ones, automatically, without operator assistance. But these
tools will still give the designer the option to get involved in
the partitioning, placement and, to a lesser extent, even
the routing of critical parts of the design, if that is needed
to optimize the performance.
On-Chip Memory
The XC4000, XC4000A and XC4000H family devices are
the first programmable logic devices with RAM accessible
to the user.
An optional mode for each CLB makes the memory look-
up tables in the F' and G' function generators usable as
either a 16 x 2 or 32 x 1 bit array of Read/Write memory
cells (Figure 3). The F1-F4 and G1-G4 inputs to the
function generators act as address lines, selecting a
particular memory cell in each look-up table. The function-
ality of the CLB control signals change in this configura-
tion; the H1, DIN, and S/R lines become the two data inputs
and the Write Enable (WE) input for the 16 x 2 memory.
When the 32 x 1 configuration is selected, D1 acts as the
fifth address bit and D0 is the data input. The contents of
the memory cell(s) being addressed are available at the F'
and G' function-generator outputs, and can exit the CLB
through its X and Y outputs, or can be pipelined using the
CLB flip-flop(s).
Configuring the CLB function generators as Read/Write
memory does not affect the functionality of the other
portions of the CLB, with the exception of the redefinition
of the control signals. The H' function generator can be
used to implement Boolean functions of F', G', and D1, and
the D flip-flops can latch the F', G', H', or D0 signals.
The RAMs are very fast; read access is the same as logic
delay, about 5.5 ns; write time is about 8 ns; both are
several times faster than any off-chip solution. Such dis-
tributed RAM is a novel concept, creating new possibilities
in system design: registered arrays of multiple accumula-
tors, status registers, index registers, DMA counters, dis-
tributed shift registers, LIFO stacks, and FIFO buffers. The
data path of a 16-byte FIFO uses four CLBs for storage,
and six CLBs for address counting and multiplexing (Fig-
ure 4). With 32 storage locations per CLB, compared to two
flip-flops per CLB, the cost of intelligent distributed memory
has been reduced by a factor of 16.
C1
C2
C3
C4
WE(S/R) D1(H1) D0(DIN)
EC
WE
G4
DATA
IN
G3
G'
Function
G2
Generator
G1
M
Write G'
M
Write F'
M
16 x 2
WE
F4
DATA
IN
F3
F'
Function
F2
Generator
F1
M Configuration Memory Bit
X6072
Figure 3. CLB Function Generators Can Be Used as
Read/Write Memory Cells
Input/Output Blocks (IOBs), XC4000 and XC4000A
Families (for XC4000H family, see page 2-82)
User-configurable IOBs provide the interface between
external package pins and the internal logic (Figure 5).
Each IOB controls one package pin and can be defined for
input, output, or bidirectional signals.
Two paths, labeled I1 and I2, bring input signals into the
array. Inputs are routed to an input register that can be
programmed as either an edge-triggered flip-flop or a
level-sensitive transparent latch. Optionally, the data input
to the register can be delayed by several nanoseconds to
compensate for the delay on the clock signal, that first must
Read
Write
Write Counter
2 CBLs
4
8
Read Counter
2 CBLs
4
8
8
Control
Full
Empty
WE
Multiplexer
2 CBLs
Data
In
Figure 4. 16-byte FIFO
2 CBLs
16 x 8 RAM
Data
Out
X5375
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