XC4000FM Datasheet, PDF (24/40 Pages) Xilinx, Inc – Flexible function generators

XC4000, XC4000A, XC4000H Logic Cell Array Families
Q3
STARTUP
Q2
*
*
*
Q1/Q4
DONE
IN
1
0
0
1
1
0
IOBs OPERATIONAL PER CONFIGURATION
GLOBAL SET/RESET OF
ALL CLB AND IOB FLIP-FLOPS
GSR ENABLE
* _{GSR INVERT}
* _STARTUP.GSR
CONTROLLED BY STARTUP SYMBOL
I^UN^ST^EH^RE^NU^ES^TER SCHEMATIC (SEE
STARTUP.GTS ^LU^IBS^RE^AR^RN^IEE^ST^GUIDE)
GTS INVERT
** _{GTS ENABLE}
GLOBAL 3-STATE OF ALL IOBs
QS
R
DONE
1
" FINISHED "
ENABLES BOUNDARY
0
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
FULL
LENGTH COUNT
Q0
SQ
K
CLEAR MEMORY
CCLK
0
STARTUP.CLK
USER NET
1
M
*
Figure 22. Start-up Logic
Q1
Q2
DQ
K
DQ
01
10
K
M
*
Q3
Q4
DQ
K
DQ
K
* ^{CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS "}
X1528
All Xilinx FPGAs of the XC2000, XC3000, XC4000 familiies
use a compatible bitstream format and can, therefore, be
connected in a daisy-chain in an arbitrary sequence. There
is however one limitation. The lead device must belong to
the highest family in the chain. If the chain contains
XC4000 devices, the master cannot be an XC2000 or
XC3000 device; if the daisy-chain contains XC3000 de-
vices, the master cannot be an XC2000 device. The
reason for this rule is shown in Figure 21 on the previous
page. Since all devices in the chain store the same length
count value and generate or receive one common se-
quence of CCLK pulses, they all recognize length-count
match on the same CCLK edge, as indicated on the left
edge of Figure 21. The master device will then drive
additional CCLK pulses until it reaches its finish point F.
The different families generate or require different num-
bers of additional CCLK pulses until they reach F.
Not reaching F means that the device does not really finish
its configuration, although DONE may have gone High, the
outputs became active, and the internal RESET was
released. The user has some control over the relative
timing of these events and can, therefore, make sure that
they occur early enough.
But, for XC4000, not reaching F means that READBACK
cannot be initiated and most Boundary Scan instructions
cannot be used.This limitation has been critized by design-
ers who want to use an inexpensive lead device in periph-
eral mode and have the more precious I/O pins of the
XC4000 devices all available for user I/O. Here is a
solution for that case.
One CLB and one IOB in the lead XC3000 device are used
to generate the additional CCLK pulse required by the
XC4000 devices. When the lead device removes the
internal RESET signal, the 2-bit shift register responds to
its clock input and generates an active Low output signal
for the duration of the subsequent clock period. An exter-
nal connection between this output and CCLK thus creates
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