XC4000FM Datasheet, PDF (12/40 Pages) Xilinx, Inc – Flexible function generators

XC4000, XC4000A, XC4000H Logic Cell Array Families
The XACT system also includes XDelay, a static timing
analyzer. XDelay examines a design’s logic and timing to
calculate the performance along signal paths, identify pos-
sible race conditions, and detect set-up and hold-time
violations. Timing analyzers do not require that the user
generate input stimulus patterns or test vectors.
Summary
The result of eight years of FPGA design experience and
feedback from thousands of customers, the XC4000 families
combine architectural versatility, on-chip RAM, increased
speed and gate complexity with abundant routing resources
and new, sophisticated software to achieve fully automated
implementation of complex, high-performance designs.
7400 Equivalents
‘138
‘139
‘147
‘148
‘150
‘151
‘152
‘153
‘154
‘157
‘158
‘160
‘161
‘162
‘163
‘164
‘165s
‘166
‘168
‘174
‘194
‘195
‘280
‘283
‘298
‘352
‘390
‘518
‘521
# of CLBs
5
2
5
6
5
3
3
2
16
2
2
5
6
8
8
4
9
5
7
3
5
3
3
8
2
2
3
3
3
Barrel Shifters
brlshft4
4
brlshft8
13
4-Bit Counters
cd4ce
3
cd4cle
5
cd4rle
6
cb4ce
3
cb4cle
6
cb4re
5
8- and 16-Bit Counters
cb8ce
6
cb8re
10
cc16ce
10
cc16cle
11
cc16cled
21
Identity Comparators
comp4
1
comp8
2
comp16
5
Magnitude Comparators
compm4
4
compm8
9
compm16
20
Decoders
d2-4e
2
d3-8e
4
d4-16e
16
Figure 10. CLB Count of Selected XC4000 Soft Macros
Multiplexers
m2-1e
1
m4-1e
1
m8-1e
3
m16-1e
5
Registers
rd4r
2
rd8r
4
rd16r
8
Shift Registers
sr8ce
4
sr16re
8
RAMs
ram 16x4
2
Explanation of counter nomenclature
cb = binary counter
cd = BCD counter
cc = cascadable binary counter
d = bidirectional
l = loadable
x = cascadable
e = clock enable
r = synchronous reset
c = asynchronous clear
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