XC4000FM Datasheet, PDF (11/40 Pages) Xilinx, Inc – Flexible function generators

comparators, counters, data registers, decoders, encod-
ers, I/O functions, latches, Boolean functions, RAM and
ROM memory blocks, multiplexers, shift registers, and
barrel shifters.
Designing with macros is as easy as designing with
standard SSI/MSI functions. The ‘soft macro’ library con-
tains detailed descriptions of common logic functions, but
does not contain any partitioning or routing information.
The performance of these macros depends, therefore, on
how the PPR software processes the design. Relationally
Placed Macros (RPMs), on the other hand, do contain pre-
determined partitioning and relative placement informa-
tion, resulting in an optimized implementation for these
functions. Users can create their own library elements –
either soft macros or RPMs – based on the macros and
primitives of the standard library.
X-BLOX is a graphics-based high-level description lan-
guage (HDL) that allows designers to use a schematic
editor to enter designs as a set of generic modules. The X-
BLOX compiler optimizes the modules for the target de-
vice architecture, automatically choosing the appropriate
architectural resources for each function.
The XACT design environment supports hierarchical de-
sign entry, with top-level drawings defining the major
functional blocks, and lower-level descriptions defining the
logic in each block. The implementation tools automati-
cally combine the hierarchical elements of a design. Differ-
ent hierarchical elements can be specified with different
design entry tools, allowing the use of the most convenient
entry method for each portion of the design.
Design Implementation
The design implementation tools satisfy the requirement
for an automated design process. Logic partitioning, block
placement and signal routing, encompassing the design
implementation process, are performed by the Partition,
Place, and Route program (PPR). The partitioner takes the
logic from the entered design and maps the logic into the
architectural resources of the FPGA (such as the logic
blocks, I/O blocks, 3-state buffers, and edge decoders).
The placer then determines the best locations for the
blocks, depending on their connectivity and the required
performance. The router finally connects the placed blocks
together. The PPR algorithms result in the fully automatic
implementation of most designs. However, for demanding
applications, the user may exercise various degrees of
control over the automated implementation process. Op-
tionally, user-designated partitioning, placement, and rout-
ing information can be specified as part of the design entry
process. The implementation of highly-structured designs
can greatly benefit from the basic floorplanning techniques
familiar to designers of large gate arrays.
The PPR program includes XACT-Performance, a feature
that allows designers to specify the timing requirements
along entire paths during design entry. Timing path analy-
sis routines in PPR then recognize and accommodate the
user-specified requirements. Timing requirements can be
entered on the schematic in a form directly relating to the
system requirements (such as the targeted minimum clock
frequency, or the maximum allowable delay on the data
path between two registers). So, while the timing of each
individual net is not predictable (nor does it need to be), the
overall performance of the system along entire signal
paths is automatically tailored to match user-generated
specifications.
The automated implementation tools are complemented
by the XACT Design Editor (XDE), an interactive graphics-
based editor that displays a model of the actual logic and
routing resources of the FPGA. XDE can be used to
directly view the results achieved by the automated tools.
Modifications can be made using XDE; XDE also performs
checks for logic connectivity and possible design-rule
violations.
Design Verification
The high development cost associated with common mask-
programmed gate arrays necessitates extensive simula-
tion to verify a design. Due to the custom nature of masked
gate arrays, mistakes or last-minute design changes can-
not be tolerated. A gate-array designer must simulate and
test all logic and timing using simulation software. Simula-
tion describes what happens in a system under worst-case
situations. However, simulation is tedious and slow, and
simulation vectors must be generated. A few seconds of
system time can take weeks to simulate.
Programmable-gate-array users, however, can use in-
circuit debugging techniques in addition to simulation.
Because Xilinx devices are reprogrammable, designs can
be verified in the system in real time without the need for
extensive simulation vectors.
The XACT development system supports both simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from
the design database. This data can then be sent to the
simulator to verify timing-critical portions of the design.
Back-annotation – the process of mapping the timing
information back into the signal names and symbols of the
schematic – eases the debugging effort.
For in-circuit debugging, XACT includes a serial download
and readback cable (XChecker) that connects the device
in the system to the PC or workstation through an RS232
serial port. The engineer can download a design or a
design revision into the system for testing. The designer
can also single-step the logic, read the contents of the
numerous flip-flops on the device and observe internal
logic levels. Simple modifications can be downloaded into
the system in a matter of minutes.
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