XC4000FM Datasheet, PDF (20/40 Pages) Xilinx, Inc – Flexible function generators

XC4000, XC4000A, XC4000H Logic Cell Array Families
11111111
0010
< 24-BIT LENGTH COUNT >
1111
0 < DATA FRAME # 001 > eeee
0 < DATA FRAME # 002 > eeee
0 < DATA FRAME # 003 > eeee
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0 < DATA FRAME # N-1 > eeee
0 < DATA FRAME # N > eeee
0111 1111
– EIGHT DUMMY BITS MINIMUM
– PREAMBLE CODE
– CONFIGURATION PROGRAM LENGTH (MSB FIRST)
– DUMMY BITS (4 BITS MINIMUM)
HEADER
(EACH FRAME CONSISTS OF:
A START BIT (0)
A DATA FIELD
FOUR ERROR CHECK BITS (eeee)
POSTAMBLE CODE
PROGRAM DATA
REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN
X1526
Device
XC4002A XC4003A XC4003/H XC4004A XC4005A XC4005/H XC4006 XC4008 XC4010/D XC4013/D XC4020 XC4025
Gates
2,000
3,000
3,000
4,000
5000
5,000
6,000
8,000
10,000 13,000 20,000 25,000
CLBs
(Row x Col)
64
100
100
144
196
196
256
324
400
576
784
1,024
(8 x 8) (10 x 10) (10 x 10) (12 x 12) (14 x 14) (14 x 14) (16 x 16) (18 x 18) (20 x 20) (24 x 24) (28 x 28) (32 x 32)
IOBs
64
80
80/.160
96
112 112 (192) 128
144
160
192
224
256
Flip-flops
256
360
360/300
480
616 616 (392) 768
936
1,120
1,536
2,016
2,560
Horizontal
TBUF Longlines 16
20
20
24
28
28
32
36
40
48
56
64
TBUFs/Longline 10
12
12
14
16
16
18
20
22
26
30
34
Bits per Frame
102
122
126
142
162
166
186
206
226
266
306
346
Frames
310
374
428
438
502
572
644
716
788
932
1,076
1,220
Program Data 31,628 45,636 53,936 62,204 81,332 94,960 119,792 147,504 178,096 247,920 329,264 422,128
PROM size (bits) 31,668 45,676 53,976 62,244 81,372 95,000 119,832 147,544 178,136 247,960 329,304 422,168
XC4000, 4000H: Bits per Frame = (10 x number of Rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of Columns) + 26 for the left edge + 41 for the right edge + 1
XC4000A:
Bits per Frame = (10 x number of Rows) + 6 for the top + 10 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (32 x number of Columns) + 21 for the left edge + 32 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40
The user can add more "one" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any
frame, following the four error check bits, but the Length Count value must be adjusted for all such extra "one" bits,
even for leading extra ones at the beginning of the header.
Figure 19. Internal Configuration Data Structure.
Format
The configuration-data stream begins with a string of ones,
a 0010 preamble code, a 24-bit length count, and a four-
bit separator field of ones. This is followed by the actual
configuration data in frames, each starting with a zero bit
and ending with a four-bit error check. For each XC4XXX
device, the MakeBits software allows a selection of CRC
or non-CRC error checking. The non-CRC error checking
tests for a 0110 end of frame field for each frame of a
selected LCA device. For CRC error checking, MakeBits
software calculates a running CRC of inserts a unique
four-bit partial check at the end of each frame. The 11-bit
CRC check of the last frame of an LCA device includes the
last seven data bits. Detection of an error results in
suspension of data loading and the pulling down of the INIT
pin. In master modes, CCLK and address signals continue
to operate externally. The user must detect INIT and
initialize a new configuration by pulsing the PROGRAM pin
or cycling V_CC. The length and number of frames depend
on the device type. Multiple LCA devices can be con-
nected in a daisy chain by wiring their CCLK pins in parallel
and connecting the DOUT of each to the DIN of the next.
The lead-master LCA device and following slaves each
passes resynchronized configuration data coming from a
single source. The Header data, including the length
count, is passed through and is captured by each LCA
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