XC4000FM Datasheet, PDF (21/40 Pages) Xilinx, Inc – Flexible function generators

Boundary Scan
Instructions
Available:
V_CC
No
>3.5 V
Yes
Test M0 Generate
One Time-Out Pulse
of 16 or 64 ms
Keep Clearing
Configuration Memory
PROGRAM
= Low
Yes
EXTEST*
SAMPLE/PRELOAD _{Completely Clear}
BYPASS
Configuration Memory
CONFIGURE*
Once More
(* if PROGRAM = High)
~1.3 µs per Frame
INIT
High? if
Master
Yes
No
Master Waits 50 to 250 µs
Before Sampling Mode Lines
Sample
Mode Lines
Master CCLK
Goes Active
Load One
Configuration
Data Frame
SAMPLE/PRELOAD
BYPASS
Frame
Yes
Error
No
Config-
uration
No
memory
Full
Yes
Pass
Configuration
Data to DOUT
Pull INIT Low
and Stop
CCLK
Count Equals ^No
Length
Count
Yes
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
Start-Up
Sequence
F
Operational
If Boundary Scan
is Selected
X6076
Figure 20. Start-up Sequence
device when it recognizes the 0010 preamble. Following
the length-count data, any LCA device outputs a High on
DOUT until it has received its required number of data
frames.
After an LCA device has received its configuration data, it
passes on any additional frame start bits and configuration
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
of the 24-bit length count, the LCA device(s) begin the
start-up sequence and become operational together.
Configuration Sequence
Configuration Memory Clear
When power is first applied or reapplied to an LCA device,
an internal circuit forces initialization of the configuration
logic. When V_CC reaches an operational level, and the
circuit passes the write and read test of a sample pair of
configuration bits, a nominal 16-ms time delay is started
(four times longer when M0 is Low, i.e., in Master mode).
During this time delay, or as long as the PROGRAM input
is asserted, the configuration logic is held in a Configura-
tion Memory Clear state. The configuration-memory frames
are consecutively initialized, using the internal oscillator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is as-
serted, the logic initiates one additional clearing of the
configuration frames and then tests the INIT input.
Initialization
During initialization and configuration, user pins HDC,
LDC and INIT provide status outputs for system interface.
The outputs, LDC, INIT and DONE are held Low and HDC
is held High starting at the initial application of power. The
open drain INIT pin is released after the final initialization
pass through the frame addresses. There is a deliberate
delay of 50 to 250 µs before a Master-mode device
recognizes an inactive INIT. Two internal clocks after the
INIT pin is recognized as High, the LCA device samples
the three mode lines to determine the configuration mode.
The appropriate interface lines become active and the
configuration preamble and data can be loaded.
Configuration
The 0010 preamble code indicates that the following
24 bits represent the length count, i.e., the total number of
configuration clocks needed to load the total configuration
data. After the preamble and the length count have been
passed through to all devices in the daisy chain, DOUT is
held High to prevent frame start bits from reaching any
daisy-chained devices. A specific configuration bit, early in
the first frame of a master device, controls the configura-
tion-clock rate and can increase it by a factor of eight. Each
frame has a Low start bit followed by the frame-configura-
2-27