XC4000FM Datasheet, PDF (1/40 Pages) Xilinx, Inc – Flexible function generators

®
XC4000, XC4000A, XC4000H
Logic Cell Array Families
Product Description
Features
Description
• Third Generation Field-Programmable Gate Arrays
– Abundant flip-flops
– Flexible function generators
– On-chip ultra-fast RAM
The XC4000 families of Field-Programmable Gate Arrays
(FPGAs) provide the benefits of custom CMOS VLSI, while
avoiding the initial cost, time delay, and inherent risk of a
conventional masked gate array.
– Dedicated high-speed carry-propagation circuit
– Wide edge decoders
The XC4000 families provide a regular, flexible, program-
mable architecture of Configurable Logic Blocks (CLBs),
– Hierarchy of interconnect lines
interconnected by a powerful hierarchy of versatile routing
– Internal 3-state bus capability
resources, and surrounded by a perimeter of program-
– Eight global low-skew clock or signal distribution
mable Input/Output Blocks (IOBs).
network
• Flexible Array Architecture
XC4000-family devices have generous routing resources to
accommodate the most complex interconnect patterns.
– Programmable logic blocks and I/O blocks
XC4000A devices have reduced sets of routing resources,
– Programmable interconnects and wide decoders
sufficient for their smaller size. XC4000H high I/O devices
• Sub-micron CMOS Process
– High-speed logic and Interconnect
maintain the same routing resources and CLB structure as
the XC4000 family, while nearly doubling the available I/O.
– Low power consumption
The devices are customized by loading configuration data
• Systems-Oriented Features
– IEEE 1149.1-compatible boundary-scan logic support
– Programmable output slew rate
– Programmable input pull-up or pull-down resistors
into the internal memory cells. The FPGA can either actively
read its configuration data out of external serial or byte-
parallel PROM (master modes), or the configuration data
can be written into the FPGA (slave and peripheral modes).
– 12-mA sink current per output (XC4000 family)
The XC4000 families are supported by powerful and so-
– 24-mA sink current per output (XC4000A and
phisticated software, covering every aspect of design: from
XC4000H families)
schematic entry, to simulation, to automatic block place-
• Configured by Loading Binary File
– Unlimited reprogrammability
ment and routing of interconnects, and finally the creation
of the configuration bit stream.
– Six programming modes
Since Xilinx FPGAs can be reprogrammed an unlimited
• XACT Development System runs on ’386/’486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
series
– Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications. FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler
Table 1. The XC4000 Families of Field-Programmable Gate Arrays
Device
XC4002A 4003/3A 4003H 4004A 4005/5A 4005H 4006 4008 4010/10D 4013/13D 4020 4025
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs
(per side)
Max RAM Bits
Number of IOBs
2,000
8x8
64
256
24
2,048
64
3,000
10 x 10
100
360
30
3,000
10 x 10
100
200
30
4,000
12 x 12
144
480
36
5,000
14 x 14
196
616
42
5,000 6,000
14 x 14 16 x 16
196 256
392 768
42
48
8,000
18 x 18
324
936
54
10,000
20 x 20
400
1,120
60
13,000
24 x 24
576
1,536
72
20,000
28 x 28
784
2,016
84
25,000
32 x 32
1,024
2,560
96
3,200 3,200 4,608 6,272 6,272 8,192 10,368 12,800* 18,432* 25,088 32,768
80
160
96
112
192 128
144
160
192 224 256
*XC4010D and XC4013D have no RAM
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