XC4000FM Datasheet, PDF (10/40 Pages) Xilinx, Inc – Flexible function generators

XC4000, XC4000A, XC4000H Logic Cell Array Families
Communication between Longlines and single-length lines
is controlled by programmable interconnect points at the
line intersections. Double-length lines do not connect to
other lines.
Three-State Buffers
A pair of 3-state buffers, associated with each CLB in the
array, can be used to drive signals onto the nearest
horizontal Longlines above and below the block. This
feature is also available in the XC3000 generation of LCA
devices. The 3-state buffer input can be driven from any
X, Y, XQ, or YQ output of the neighboring CLB, or from
nearby single-length lines; the buffer enable can come
from nearby vertical single-length or Longlines. Another 3-
state buffer with similar access is located near each I/O
block along the right and left edges of the array. These
buffers can be used to implement multiplexed or bidirec-
tional buses on the horizontal Longlines. Programmable
pull-up resistors attached to both ends of these Longlines
help to implement a wide wired-AND function.
Special Longlines running along the perimeter of the array
can be used to wire-AND signals coming from nearby IOBs
or from internal Longlines.
Taking Advantage of Reconfiguration
LCA devices can be reconfigured to change logic function
while resident in the system. This gives the system de-
signer a new degree of freedom, not available with any
other type of logic. Hardware can be changed as easily as
software. Design updates or modifications are easy. An
LCA device can even be reconfigured dynamically to
perform different functions at different times. Reconfigurable
logic can be used to implement system self diagnostics,
create systems capable of being reconfigured for different
environments or operations, or implement dual-purpose
hardware for a given application. As an added benefit, use
of reconfigurable LCA devices simplifies hardware design
and debugging and shortens product time-to-market.
Development System
The powerful features of the XC4000 device families
require an equally powerful, yet easy-to-use set of devel-
opment tools. Xilinx provides an enhanced version of the
Xilinx Automatic CAE Tools (XACT) optimized for the
XC4000 families.
As with other logic technologies, the basic methodology for
XC4000 FPGA design consists of three inter-related steps:
entry, implementation, and verification. Popular ‘generic’
tools are used for entry and simulation (for example,
Viewlogic System’s ViewDraw schematic editor and
ViewSim simulator), but architecture-specific tools are
needed for implementation.
All Xilinx development system software is integrated under
the Xilinx Design Manager (XDM), providing designers
with a common user interface regardless of their choice of
entry and verification tools. XDM simplifies the selection of
command-line options with pull-down menus and on-line
help text. Application programs ranging from schematic
capture to Partitioning, Placement, and Routing (PPR) can
be accessed from XDM, while the program-command
sequence is generated and stored for documentation prior
to execution. The XMAKE command, a design compilation
utility, automates the entire implementation process, auto-
matically retrieving the design’s input files and performing
all the steps needed to create configuration and report
files.
Several advanced features of the XACT system facilitate
XC4000 FPGA design. The MEMGEN utility, a memory
compiler, implements on-chip RAM within an XC4000
FPGA. Relationally Placed Macros (RPMs) – schematic-
based macros with relative locations constraints to guide
their placement within the FPGA – help ensure an opti-
mized implementation for common logic functions. XACT-
Performance, a feature of the Partition, Place, and Route
(PPR) implementation program, allows designers to enter
their exact performance requirements during design entry,
at the schematic level.
Design Entry
Designs can be entered graphically, using schematic-
capture software, or in any of several text-based formats
(such as Boolean equations, state-machine descriptions,
and high-level design languages).
Xilinx and third-party CAE vendors have developed library
and interface products compatible with a wide variety of
design-entry and simulation environments. A standard
interface-file specification, XNF (Xilinx Netlist File), is
provided to simplify file transfers into and out of the XACT
development system.
Xilinx offers XACT development system interfaces to the
following design environments.
• Viewlogic Systems (ViewDraw, ViewSim)
• Mentor Graphics V7 and V8 (NETED, Quicksim,
Design Architect, Quicksim II)
• OrCAD (SDT , VST)
• Synopsys (Design Compiler, FPGA Compiler)
• Xilinx-ABEL
• X-BLOX
Many other environments are supported by third-party
vendors. Currently, more than 100 packages are sup-
ported.
The schematic library for the XC4000 FPGA reflects the
wide variety of logic functions that can be implemented in
these versatile devices. The library contains over 400
primitives and macros, ranging from 2-input AND gates to
16-bit accumulators, and including arithmetic functions,
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