XC4000FM Datasheet, PDF (2/40 Pages) Xilinx, Inc – Flexible function generators

XC4000, XC4000A, XC4000H Logic Cell Array Families
XC4000 Compared to XC3000A
For those readers already familiar with the XC3000A
family of Xilinx Field Programmable Gate Arrays, here is a
concise list of the major new features in the XC4000 family.
CLB has two independent 4-input function generators.
A third function generator combines the outputs of the
two other function generators with a ninth input.
All function inputs are swappable, all have full access;
none are mutually exclusive.
CLB has very fast arithmetic carry capability.
CLB function generator look-up table can also be used as
high-speed RAM.
CLB flip-flops have asynchronous set or reset.
CLB has four outputs, two flip-flops, two combinatorial.
CLB connections symmetrically located on all four edges.
IOB has more versatile clocking polarity options.
IOB has programmable input set-up time:
long to avoid potential hold time problems,
short to improve performance.
IOB has Longline access through its own TBUF.
Outputs are n-channel only, lower V_OH increases speed.
XC4000 outputs can be paired to double sink current to
24 mA. XC4000A and XC4000H outputs can each
sink 24 mA, can be paired for 48 mA sink current.
IEEE 1149.1- type boundary scan is supported in the I/O.
Wide decoders on all four edges of the LCA device.
Increased number of interconnect resources.
All CLB inputs and outputs have access to most inter-
connect lines.
Switch Matrices are simplified to increase speed.
Eight global nets can be used for clocking or distributing
logic signals.
TBUF output configuration is more versatile and 3-state
control less confined.
Program is single-function input pin,overrides everything.
INIT pin also acts as Configuration Error output.
Peripheral Synchronous Mode (8 bit) has been added.
Peripheral Asynchronous Mode has improved hand-
shake.
Start-up can be synchronized to any user clock (this is a
configuration option).
No Powerdown, but instead a Global 3-state input that
does not reset any flip-flops.
No on-chip crystal oscillator amplifier.
Configuration Bit Stream includes CRC error checking.
Configuration Clock can be increased to >8 MHz.
Configuration Clock is fully static, no constraint on the
maximum Low time.
Readback either ignores flip-flop content (avoids need for
masking) or it takes a snapshot of all flip-flops at the
start of Readback.
Readback has same polarity as Configuration and can be
aborted.
Table 2. Three Generations of Xilinx Field-Programmable Gate Array Families
Parameter
XC4025
XC3195A
Number of flip-flops
Max number of user I/O
Max number of RAM bits
Function generators per CLB
Number of logic inputs per CLB
Number of logic outputs per CLB
Number of low-skew global nets
Dedicated decoders
Fast carry logic
Internal 3-state drivers
Output slew-rate control
Power-down option
Crystal oscillator circuit
2,560
256
32,768
3
9
4
8
yes
yes
yes
yes
no
no
1,320
176
0
2
5
2
2
no
no
yes
yes
yes
yes
XC2018
174
74
0
2
4
2
2
no
no
no
no
yes
yes
2-8