XC4000FM Datasheet, PDF (25/40 Pages) Xilinx, Inc – Flexible function generators

Reset
00
10
11
01
01
.. ^etc ..
Active Low Output
Active High Output
OE/T
Output
Connected
to CCLK
X5223
the extra CCLK pulse. This solution requires one CLB, one
IOB and pin, and an internal oscillator with a frequency of
up to 5 MHz as available clock source. Obviously, this
XC3000 master device must be configured with late Inter-
nal Reset, which happens to be the default option.
Using Global Set/Reset and Global 3-State Nets
The global Set/Reset (STARTUP.GSR) net can be driven
by the user at any time to re-initialize all CLBs and IOBs to
the same state they had at the end of configuration. For
CLBs that is the same state as the one driven by the
individually programmable asynchronous Set/Reset in-
puts. The global 3-state net (STARTUP.GTS), whenever
activated after configuration is completed, forces all LCA
outputs to the high-impedance state, unless Boundary
Scan is enabled and is executing an EXTEST instruction.
Readback
The user can read back the content of configuration
memory and the level of certain internal nodes without
interfering with the normal operation of the device.
Readback reports not only the downloaded configuration
bits, but can also include the present state of the device
represented by the content of all used flip-flops and latches
in CLBs and IOBs, as well as the content of function
generators used as RAMs.
XC4000 Readback does not use any dedicated pins, but
uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK ) that can be routed to any IOB.
After Readback has been initiated by a Low-to-High tran-
sition on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net. Readback data does not
include the preamble, but starts with five dummy bits (all
High) followed by the Start bit (Low) of the first frame. The
first two data bits of the first frame are always High.
Note that, in the XC4000 families, data is not inverted with
respect to configuration the way it is in XC2000 and
XC3000 families.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RIP returns Low.
Readback options are: Read Capture, Read Abort, and
Clock Select.
Read Capture
When the Readback Capture option is selected, the
readback data stream includes sampled values of CLB
and IOB signals imbedded in the data stream. The rising
edge of RDBK.TRIG located in the lower-left chip corner,
captures, in latches, the inverted values of the four CLB
outputs and the IOB output flip-flops and the input signals
I1, I2 . When the capture option is not selected, the values
of the capture bits reflect the configuration data originally
written to those memory locations. If the RAM capability of
the CLBs is used, RAM data are available in readback,
since they directly overwrite the F and G function-table
configuration of the CLB.
Read Abort
When the Readback Abort option is selected, a High-to-
Low transition on RDBK.TRIG terminates the readback
operation and prepares the logic to accept another trigger.
After an aborted readback, additional clocks (up-to-one
readback clock per configuration frame) may be required
to re-initialize the control logic. The status of readback is
indicated by the output control net (RDBK.RIP).
Clock Select
Readback control and data are clocked on rising edges of
RDBK.CLK located in the lower right chip corner. CCLK is
an optional clock. If Readback must be inhibited for secu-
rity reasons, the readback control nets are simply not
connected.
XChecker
The XChecker Universal Download/Readback Cable and
Logic Probe uses the Readback feature for bitstream
verification and for display of selected internal signals on
the PC or workstation screen, effectively as a low-cost in-
circuit emulator.
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