XC4000FM Datasheet, PDF (31/40 Pages) Xilinx, Inc – Flexible function generators

Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration, causes the LCA
device to wait after having completed the configuration
memory clear operation. When INIT is no longer held Low
externally, the device determines its configuration mode by
capturing its status inputs, and is ready to start the configura-
tion process. A master device waits an additional max 250 µs
to make sure that all slaves in the potential daisy-chain have
seen INIT being High.
Master Parallel Mode Programming Switching Characteristics
A0-A17
(output)
Address for Byte n
D0-D7
RCLK
(output)
CCLK
(output)
Byte
2 T_DRC
7 CCLKs
Address for Byte n + 1
1 T_RAC
3 T_RCD
CCLK
DOUT
(output)
D6
Byte n - 1
D7
X6078
RCLK
Description
Symbol
Min
Delay to Address valid
1 T_RAC
0
Data setup time
2 T_DRC
60
Data hold time
3 T_RCD
0
Max
Units
200
ns
ns
ns
Notes: 1. At power-up, V_CC must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration using PROGRAM
until V_CC is valid.
2. Configuration can be delayed by holding INIT Low with or until after the INIT of all daisy-chain slave mode devices
is High.
3. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
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