XC4000FM Datasheet, PDF (23/40 Pages) Xilinx, Inc – Flexible function generators

Length Count Match
CCLK Period
CCLK
XC2000
DONE
I/O
Global Reset
XC3000
DONE
I/O
F
F
Global Reset
F
DONE
C1
C2
C3
C4
XC4000
I/O
CCLK_NOSYNC
C2
C3
C4
GSR Active
C2
C3
C4
DONE IN
F
DONE
XC4000
CCLK_SYNC
C1, C2 or C3
I/O
Di
Di+1
GSR Active
Di Di+1
F
DONE
C1
XC4000
I/O
UCLK_NOSYNC
U2
U3
U4
U2
U3
U4
GSR Active
DONE
C1
XC4000
I/O
UCLK_SYNC
U2
U3
U4
DONE IN
F
U2
Di Di+1
Di+2
GSR Active
Synchronization
Uncertainty
Di Di+1
Di+2
UCLK Period
Note: Thick lines are default option.
Figure 21. Start-up Timing
2-29
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
X3459