XC4000FM Datasheet, PDF (33/40 Pages) Xilinx, Inc – Flexible function generators

Synchronous Peripheral Mode Programming Switching Characteristics
CCLK
INIT
DOUT
BYTE
0
BYTE
1
BYTE 0 OUT
BYTE 1 OUT
0
1
2
3
4
5
6
7
0
1
RDY/BUSY
Description
Symbol
Min
Max
X6096
Units
CCLK
INIT (High) Setup time required
1 T_IC
5
D0-D7 Setup time required
2 T_DC
60
D0-D7 Hold time required
3 T_CD
0
CCLK High time
T_CCH
50
CCLK Low time
T_CCL
60
CCLK Frequency
F_CC
µs
ns
ns
ns
ns
8
MHz
Notes:
Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in
the first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on
every eighth consecutive rising edge of CCLK.
The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation
does not require such a response.
The pin name RDY/BUSY is a misnomer; in Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
Note that data starts to shift out serially on the DOUT pin 0.5 CLK periods after it was loaded in parallel. This obviously
requires additional CCLK pulses after the last byte has been loaded.
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