XC4000FM Datasheet, PDF (27/40 Pages) Xilinx, Inc – Flexible function generators

externally, the device determines its configuration mode
by capturing its status inputs, and is ready to start the
configuration process. A master device waits an additional
up to 250 µs to make sure that all slaves in the potential
daisy-chain have seen INIT being High.
Master Serial Mode Programming Switching Characteristics
CCLK
(Output)
Serial Data In
1 ^TDSCK
n
2 ^TCKDS
n+1
n+2
Serial DOUT
(Output)
n–3
n–2
n–1
n
X3223
CCLK
Description
Data In setup
Data In hold
Symbol
Min
1
T_DSCK
20
2
T_CKDS
0
Max
Units
ns
ns
Notes: 1. At power-up, V_CC must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling
PROGRAM Low until V_CC is valid.
2. Configuration can be controlled by holding INIT Low with or until after the INIT of all daisy-chain slave mode devices
is High.
3. Master-serial-mode timing is based on testing in slave mode.
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