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XC4000FM Datasheet, PDF (13/40 Pages) Xilinx, Inc – Flexible function generators
Detailed Functional Description
XC4000 and XC4000A Input/Output Blocks
(For XC4000H family, see page 2-82)
The IOB forms the interface between the internal logic and
the I/O pads of the LCA device. Under configuration con-
trol, the output buffer receives either the logic signal (.out)
routed from the internal logic to the IOB, or the complement
of this signal, or this same data after it has been clocked
into the output flip-flop.
As a configuration option, each flip-flop (CLB or IOB) is
initialized as either set or reset, and is also forced into this
programmable initialization state whenever the global Set/
Reset net is activated after configuration has been com-
pleted. The clock polarity of each IOB flip-flop can be
configured individually, as can the polarity of the 3-state
control for the output buffer.
Each output buffer can be configured to be either fast or
slew-rate limited, which reduces noise generation and
ground bounce. Each I/O pin can be configured with either
an internal pull-up or pull down resistor, or with no internal
resistor. Independent of this choice, each IOB has a pull-
up resistor during the configuration process.
The 3-state output driver uses a totem pole n-channel
output structure. VOH is one n-channel threshold lower
than VCC, which makes rise and fall delays more
symmetrical.
Family
Per IOB Per IOB Per IOB # Slew
Source Sink Pair Sink Modes
XC4000
XC4000A
XC4000H
4
12
24
2
4
24
48
4
4
24*
48
2
*XC4000H devices can sink only 4 mA configured for SoftEdge mode
3-State TS
OUTPUT
Ouput Data O
Ouput Clock OK
TS INV M
TS/OE
Boundary
Scan
TS - capture
TS - update
INVERT
OUTPUT
M
sd
DQ
M INVERT
rd
M S/R
EXTEST
SLEW
RATE
PULL
DOWN
PULL
UP
VCC
M
PAD
OUT
SEL
Boundary
Scan
O - capture
Q - capture
O - update
Boundary
Scan
I - capture
I - update
Input Clock IK
DELAY
M
INPUT
sd
DQ
M INVERT
QL
rd
M S/R
MM
MM
FLIP-FLOP/LATCH
GLOBAL
S/R
Figure 11. XC4000 and XC4000A I/O Block
2-19
Input Data 1 I1
Input Data 2 I2
X3025