XC4000FM Datasheet, PDF(16/40 Page) Xilinx, Inc

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XC4000FM Datasheet, PDF (16/40 Pages) Xilinx, Inc – Flexible function generators

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XC4000, XC4000A, XC4000H Logic Cell Array Families

Boundary Scan

Boundary Scan is becoming an attractive feature that

helps sophisticated systems manufacturers test their PC

boards more safely and more efficiently. The XC4000

family implements IEEE 1149.1-compatible BYPASS,

PRELOAD/SAMPLE and EXTEST Boundary-Scan instruc-

tions. When the Boundary-Scan configuration option is

selected, three normal user I/O pins become dedicated

inputs for these functions.

The âbed of nailsâ has been the traditional method of

testing electronic assemblies. This approach has become

less appropriate, due to closer pin spacing and more

sophisticated assembly methods like surface-mount tech-

nology and multi-layer boards. The IEEE Boundary Scan

standard 1149.1 was developed to facilitate board-level

testing of electronic assemblies. Design and test engi-

neers can imbed a standard test logic structure in their

electronic design. This structure is easily implemented

with the serial and/or parallel connections of a four-pin

interface on any Boundary-Scan-compatible IC. By exer-

cising these signals, the user can serially load commands

and data into these devices to control the driving of their

outputs and to examine their inputs. This is an improve-

ment over bed-of-nails testing. It avoids the need to over-

drive device outputs, and it reduces the user interface to

four pins. An optional fifth pin, a reset for the control logic,

is described in the standard but is not implemented in the

Xilinx part.

The dedicated on-chip logic implementing the IEEE 1149.1

functions includes a 16-state machine, an instruction reg-

ister and a number of data registers. A register operation

begins with a capture where a set of data is parallel loaded

into the designated register for shifting out. The next state

is shift, where captured data are shifted out while the

desired data are shifted in. A number of states are provided

for Wait operations. The last state of a register sequence

is the update where the shifted content of the register is

loaded into the appropriate instruction- or data-holding

The primary data register is the Boundary-Scan register.

For each IOB pin in the LCA device, it includes three bits

of shift register and three update latches for: in, out and 3-

state control. Non-IOB pins have appropriate partial bit

population for in or out only. Each Extest Capture captures

all available input pins.

The other standard data register is the single flip-flop

bypass register. It resynchronizes data being passed

through a device that need not be involved in the current

scan operation. The LCA device provides two user nets

(BSCAN.SEL1 and BSCAN.SEL2) which are the decodes

of two user instructions. For these instructions, two corre-

sponding nets (BSCAN.TDO1 and BSCAN.TDO2) allow

user scan data to be shifted out on TDO. The data register

clock (BSCAN.DRCK) is available for control of test logic

which the user may wish to implement with CLBs. The

NAND of TCK and Run-test-idle is also provided

(BSCAN.IDLE).

The XC4000 Boundary Scan instruction set also includes

instructions to configure the device and read back the con-

figuration data.

Table 4. Boundary Scan Instruction

Instruction

I2 I1 I0

000

001

010

011

100

101

110

111

Test

Selected

TDO

Source

Extest

Sample/Preload

User 1

TDO1

User 2

TDO2

Readback Readback Data

Configure

DOUT

Reserved

Bypass

Bypass Reg

I/O Data

Source

Pin/Logic

Disabled

Pin/Logic

X2679

Bit Sequence

The bit sequence within each IOB is: in, out, 3-state.

From a cavity-up (XDE) view of the chip, starting in the

upper right chip corner, the Boundary-Scan data-register

bits have the following order.

Table 5. Boundary Scan Order

Bit 0 ( TDO end)

Bit 1

Bit 2

TDO.T

TDO.O

Top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom)

MD1.T

MD1.O

MD1.I

MD0.I

MD2.I

Bottom-edge IOBs (Left to Right)

(TDI end)

Right-edge IOBs (Bottom to Top)

B SCANT.UPD

X6075

The data register also includes the following non-pin bits:

TDO.T, and TDO.I, which are always bits 0 and 1 of the

data register, respectively, and BSCANT.UPD which is

always the last bit of the data register. These three Bound-

ary-Scan bits are special-purpose Xilinx test signals. PRO-

GRAM, CCLK and DONE are not included in the Bound-

ary-Scan register. For more information regarding Bound-

ary Scan, refer to XAPP 017.001, Boundary Scan in

XC4000 Devices.

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