XC4000FM Datasheet, PDF (18/40 Pages) Xilinx, Inc – Flexible function generators

XC4000, XC4000A, XC4000H Logic Cell Array Families
Interconnects
The XC4000 families use a hierarchy of interconnect
resources.
• General purpose single-length and double-length
lines offer fast routing between adjacent blocks, and
highest flexibility for complex routes, but they incur a
delay every time they pass through a switch matrix.
• Longlines run the width or height of the chip with
negligible delay variations. They are used for signal
distribution over long distances. Some Horizontal
Longlines can be driven by 3-state or open-drain
drivers, and can thus implement bidirectional buses
or wired-AND decoding.
• Global Nets are optimized for the distribution of clock
and time-critical or high-fan-out control signal. Four
pad-driven Primary Global Nets offer shortest delay
and negligible skew. Four pad-driven Secondary
Global Nets have slightly longer delay and more
skew due to heavier loading.
Each CLB column has four dedicated Vertical Longlines,
each of these lines has access to a particular Primary
Global Net, or to any one of the Secondary Global Nets.
The Global Nets avoid clock skew and potential hold-time
SECONDARY
GLOBAL NETS
PRIMARY
GLOBAL NETS
X1027
Figure 17. XC4000 Global Net Distribution. Four Lines per
Column; Eight Inputs in the Four Chip Corners.
problems. The user must specify these Global Nets for all
timing-sensitive global signal distribution.
+5 V
~5 kΩ
Z = D_A • D_B • ( D_C +D_D ) • (DE +D F ) …
+5 V
~5 kΩ
D_A
D_B
D_C
D_D
D_E
D_F
X1006
Open Drain Buffers Implement a Wired-AND Function. When all the buffer
inputs are High the pull-up resistor(s) provide the High output.
~100 kΩ
Z = D_A • A + D_B • B + D_C • C + … + D_N • N
D_A
D_B
D_C
D_N
“KEEPER”
A
B
C
N
X1007
3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
T
OE
Active High T is Identical to
Active Low Output Enable.
Figure 18. TBUFs Driving Horizontal Longlines.
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