XC4000FM Datasheet, PDF (30/40 Pages) Xilinx, Inc – Flexible function generators

XC4000, XC4000A, XC4000H Logic Cell Array Families
Master Parallel Mode
GENERAL-
PURPOSE
USER I/O
PINS
PROGRAM
HIGH
or
LOW
+5 V
M0 M1 M2
DOUT
CCLK
A17
HDC
A16
LDC
A15
RCLK
A14
INIT
A13
A12
OTHER
I/O PINS
A11
A10
PROGRAM
A9
D7
A8
D6 XC4000
A7
D5
A6
D4
A5
D3
A4
D2
A3
D1
A2
D0
A1
A0
DONE
TO DIN OF OPTIONAL
DAISY-CHAINED
LCA DEVICES WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
DAISY-CHAINED
LCA DEVICES WITH
DIFFERENT CONFIGURATIONS
...
...
...
...
...
EPROM
(8K x 8)
(OR LARGER)
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIVE CONFIGURATIONS
A10
A9
A8
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
OE
CE
8
DATA BUS
X3394
In Master Parallel mode, the lead LCA device directly ad-
dresses an industry-standard byte-wide EPROM, and ac-
cepts eight data bits right before incrementing (or
decrementing) the address outputs.
The eight data bits are serialized in the lead LCA device,
which then presents the preamble data ( and all data that
overflows the lead device ) on the DOUT pin. There is an
internal delay of 1.5 CCLK periods, after the rising CCLK
edge that accepts a byte of data (and also changes the
EPROM address) until the falling CCLK edge that makes
the LSB (D0) of this byte appear at DOUT. This means that
DOUT changes on the falling CCLK edge, and the next
LCA device in the daisy-chain accepts data on the subse-
quent rising CCLK edge.
How to Delay Configuration After Power-Up
There are two methods to delay configuration after power-
up: Put a logic Low on the PROGRAM input, or pull the
bidirectional INIT pin Low, using an open-collector (open-
drain) driver. (See also Figure 20 on page 2-27).
A Low on the PROGRAM input is the more radical ap-
proach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the XC4000 device keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output.
2-36