XC4000FM Datasheet, PDF (36/40 Pages) Xilinx, Inc – Flexible function generators

XC4000, XC4000A, XC4000H Logic Cell Array Families
General LCA Switching Characteristics
Vcc
PROGRAM
INIT
X1532
T _POR
T _PI
CCLK OUTPUT or INPUT
M0, M1, M2
(Required)
T_ICCK
VALID
Master Modes
Power-On-Reset
Program Latency
M0 = High
M0 = Low
Symbol
T_POR
T_POR
T_PI
CCLK (output) Delay
period (slow)
period (fast)
T_ICCK
T_CCLK
T_CCLK
Slave and Peripheral Modes
Power-On-Reset
Program Latency
Symbol
T_POR
T_PI
CCLK (input) Delay (required)
period (required)
T_ICCK
T_CCLK
Note: At power-up, V_CC must rise from 2.0 V to V_CC min in less than 25 ms,
otherwise delay configuration using PROGRAM until V_CC is valid.
RE-PROGRAM
>300 ns
T_CCLK
DONE RESPONSE
I/O
<300 ns
<300 ns
Min
10
40
30
40
640
100
Max
40
130
200
250
2000
250
Units
ms
ms
µs per
CLB column
µs
ns
ns
Min
10
30
4
100
Max
33
200
Units
ms
µs per
CLB column
µs
ns
2-42