XC4000FM Datasheet, PDF (35/40 Pages) Xilinx, Inc – Flexible function generators

A Low on the PROGRAM input is the more radical ap-
proach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the XC4000 device keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration, causes the LCA
device to wait after having completed the configuration
memory clear operation. When INIT is no longer held Low
externally, the device determines its configuration mode
by capturing its status inputs, and is ready to start the
configuration process. A master device waits an additional
max 250 µs to make sure that all slaves in the potential
daisy-chain have seen INIT being High.
Asynchronous Peripheral Mode Programming Switching Characteristics
Write to LCA
Read Status
WS/CS0
RS, CS0
RS, CS1
D0-D7
CCLK
RDY/BUSY
1 _TCA
2 _TDC
3 _TCD
T_WTRB ⁴
6 _TBUSY
WS, CS1
7
4
READY
BUSY
D7
DOUT
Previous Byte D6
Description
D7
Symbol
D0
Min
D1
D2
Max
X6097
Units
Write
Effective Write time required
1 T_CA
100
ns
(CS0, WS = Low, RS, CS1 = High)
DIN Setup time required
DIN Hold time required
2 T_DC
60
3 T_CD
0
RDY/BUSY delay after end of
Write or Read
RDY/BUSY active after begining of
Read
4
T_WTRB
7
ns
ns
60
ns
60
ns
RDY
Earliest next WS after end of BUSY
5
T_RBWT
0
BUSY Low output (Note 4)
6
T_BUSY
2
ns
9
CCLK
Periods
Notes:
1. Configuration must be delayed until the INIT of all LCA devices is High.
2. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and
the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data.
The shortest TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs
when a new word is loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relaxed requirements:
Data need not be held beyond the rising edge of WS. BUSY will go active within 60 ns after the end of WS.
WS may be asserted immediately after the end of BUSY.
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