W83627EHF Datasheet, PDF (98/141 Pages) Winbond – evolving product from Winbonds most popular I/O family

W83627EHF/EF, W83627EHG/EG
CR 24h. (Global Option; Default 0100_0ss0b)
s: value by strapping
BIT READ / WRITE
DESCRIPTION
7 Reserved.
CLKSEL => Input clock rate selection
6
R/W
= 0 The clock input on pin18 is 24MHz.
= 1 The clock input on pin18 is 48MHz. (Default)
5 Reserved.
Enable SYSFANOUT as Output Buffer (For H version only)
4
R/W
=0 SYSFANOUT is Open-Drain. (Default)
=1 SYSFANOUT can drive logical high or logical low.
Enable CPUFANOUT0 as Output Buffer (For H version only)
3
R/W
=0 CPUFANOUT0 is Open-Drain. (Default)
=1 CPUFANOUT0 can drive logical high or logical low.
ENKBC => Enable keyboard controller
= 0 KBC is disabled after hardware reset.
2
Read Only _{= 1 KBC is enabled after hardware reset.}
This bit is read only, and set/reset by power-on strapping pin (PIN54;
SOUTA).
ENROM => Enable Serial FHW
= 0 ROM is disabled after hardware reset.
1
R/W
= 1 ROM is enabled after hardware reset.
This bit set/reset by power-on strapping pin (PIN52; DTRA).
PNPCVS =>
0
R/W
= 0 The compatible PNP address select registers have default values.
= 1 The compatible PNP address select registers have no default
value.
CR 25h. (Interface tri-state Enable; Default 00h)
BIT READ / WRITE
7~6 Reserved.
5
R/W
URBTRI
4
R/W
URATRI
3
R/W
PRTTRI
2~1 Reserved.
0
R/W
FDCTRI.
DESCRIPTION
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