W83627EHF Datasheet, PDF (61/141 Pages) Winbond – evolving product from Winbonds most popular I/O family

W83627EHF/EF, W83627EHG/EG
7 6 5 4 32 1 0
PWM_SCALE3
PWM_CLK_SEL3
The register is meaningful when AUXFANOUT be programmed as PWM output.
Bit 7: AUXFANOUT PWM Input Clock Source Select. This bit selects the clock source of PWM output
frequency.
Set to 0, select 24 MHz.
Set to 1, select 180 KHz.
Bit 6-0: AUXFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output
frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0.
01h : divider is 1
02h : divider is 2
03h : divider is 3
:
:
the formula is
Input Clock
1
PWM output frequency = _{Pre_Scale Divider} ∗ ₂₅₆
6.8.20 AUXFANOUT Output Value Select Register - Index 11h (Bank 0)
Register Location:
11h
Power on Default Value:
FFh
Attribute:
Read/Write
Size:
8 bits
7 6 5 4 32 1 0
AUXFANOUT Value
(1)If AUXFANOUT be programmed as PWM output (Bank0 Index 12h.bit0 is 0)
Publication Release Date: January 18, 2006
-55-
Revision 1.0