W83627EHF Datasheet, PDF (79/141 Pages) Winbond – evolving product from Winbonds most popular I/O family

W83627EHF/EF, W83627EHG/EG
7 6 5 4 32 1 0
PWM_SCALE4
PWM_CLK_SEL4
The register is meaningful when CPUFANOUT1 be programmed as PWM output.
Bit 7: CPUFANOUT1 PWM Input Clock Source Select. This bit selects the clock source of PWM
output frequency.
Set to 0, select 24 MHz.
Set to 1, select 180 KHz.
Bit 6-0: CPUFANOUT1 PWM Pre-Scale divider. This is the divider of clock source of PWM output
frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0.
01h : divider is 1
02h : divider is 2
03h : divider is 3
:
:
the formula is
PWM
output
frequency =
Input Clock
Pre_Scale Divider
∗
1
256
6.8.57 CPUFANOUT1 Output Value Select Register - Index 61h (Bank 0)
Register Location:
61h
Power on Default Value:
FFh
Attribute:
Read/Write
Size:
8 bits
7 6 5 4 32 1 0
CPUFANOUT1 Value
(1)If CPUFANOUT1 be programmed as PWM output (Bank0 Index 62h.bit6 is 0)
Bit 7-0: CPUFANOUT1 PWM Duty Cycle. Write FFh, CPUFANOUT1 duty cycle is 100%. Write 00h,
CPUFANOUT1 duty cycle is 0%.
Publication Release Date: January 18, 2006
-73-
Revision 1.0