W83627EHF Datasheet, PDF (68/141 Pages) Winbond – evolving product from Winbonds most popular I/O family

W83627EHF/EF, W83627EHG/EG
Bit 7: A one restores power on default value to some registers. This bit clears itself since the power on
default is zero.
Bit 6: Reserved
Bit 5: Reserved
Bit 4: Reserved
Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The
device will stop monitoring. It will resume upon clearing of this bit.
Bit 2: Reserved
Bit 1: A one enables the SMI# Interrupt output.
Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode.
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an
interrupt has occurred unlike "INT_Clear'' bit.
6.8.33 Interrupt Status Register 1 - Index 41h (Bank 0)
Register Location:
41h
Power on Default Value:
00h
Attribute:
Read Only
Size:
8 bits
7 6 5 4321 0
CPUVCORE
VIN0
AVCC(Pin114)
3VCC
SYSTIN
CPUTIN
SYSFANIN
CPUFANIN0
Bit 7: A one indicates the fan count limit of CPUFANIN0 has been exceeded.
Bit 6: A one indicates the fan count limit of SYSFANIN has been exceeded.
Bit 5: A one indicates a High limit of CPUTIN temperature has been exceeded.
Bit 4: A one indicates a High limit of SYSTIN temperature has been exceeded .
Bit 3: A one indicates a High or Low limit of 3VCC has been exceeded.
Bit 2: A one indicates a High or Low limit of AVCC has been exceeded.
Bit 1: A one indicates a High or Low limit of VIN0 has been exceeded.
Bit 0: A one indicates a High or Low limit of CPUVCORE has been exceeded.
6.8.34 Interrupt Status Register 2 - Index 42h (Bank 0)
Register Location:
42h
Power on Default Value:
00h
Attribute:
Read Only
Size:
8 bits
-62-