W83627EHF Datasheet, PDF (71/141 Pages) Winbond – evolving product from Winbonds most popular I/O family

W83627EHF/EF, W83627EHG/EG
Bit 7-6: CPUFANIN0 Divisor bit1:0.
Bit 5-4: SYSFANIN Divisor bit1:0.
Bit 3: CPUFANIN1 output value if bit 0 sets to 0. Write 1, pin119(CPUFANIN1) always generates a
logic high signal. Write 0, pin119 always generates a logic low signal. This bit is default 0.
Bit 2: CPUFANIN1 Input Control. Set to 1, pin119 (CPUFANIN1) acts as FAN tachometer input, which
is default value. Set to 0, this pin119 acts as FAN control signal and the output value of FAN
control is set by this register bit 1.
Bit 1: AUXFANIN1 output value if bit 0 sets to 0. Write 1, pin58(AUXFANIN1) always generates a logic
high signal. Write 0, pin58 always generates a logic low signal. This bit is default 0.
Bit 0: AUXFANIN1 Input Control. Set to 1, pin58 (AUXFANIN1) acts as FAN tachometer input, which is
default value. Set to 0, this pin58 acts as FAN control signal and the output value of FAN
control is set by this register bit 1.
Note : Please refer to Bank0 Index 5Dh , Fan divisor table.
6.8.40 Serial Bus Address Register - Index 48h (Bank 0)
Register Location:
48h
Power on Default Value:
2Dh
Attribute:
Read/Write
Size:
8 bits
7 654 32 1 0
Serial Bus Addr.
Bit 7: Reserved (Read Only).
Bit 6-0: Serial Bus address <7:1>.
Reserved
6.8.41 Reserved - Index 49h (Bank 0)
6.8.42 CPUFANOUT1 with Temperature source Select - Index 4Ah (Bank 0)
Register Location:
4Ah
Power on Default Value:
64h
Attribute:
Read/Write
Size:
8 bits
Publication Release Date: January 18, 2006
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Revision 1.0