W83627EHF Datasheet, PDF (70/141 Pages) Winbond – evolving product from Winbonds most popular I/O family

W83627EHF/EF, W83627EHG/EG
7 6 54321 0
VIN1
VIN3
VIN2
AUXFANIN0
CASEOPEN
AUXTIN
TAR1
TAR2
Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt.
6.8.37 Reserved Register - Index 45h (Bank 0)
6.8.38 SMI# Mask Register 3 - Index 46h (Bank 0)
Register Location:
46h
Power on Default Value:
07h
Attribute:
Read/Write
Size:
8 bits
7 6 54321 0
VIN4
CPUFANIN1
AUXFANIN1
Reserved
Reserved
Reserved
Reserved
CaseOpen Clear
Bit 7: CASEOPEN Clear Control. Write 1 to this bit will clear CASEOPEN status. This bit won’t be self
cleared, please write 0 after event be cleared. The function is as same as LDA, CR[E6h] bit 5.
Bit 6-3: Reserved.
Bit 2-0: A one disables the corresponding interrupt status bit for SMI interrupt.
6.8.39 Fan Divisor Register I - Index 47h (Bank 0)
Register Location:
47h
Power on Default Value:
55h
Attribute:
Read/Write
Size:
8 bits
7 654 32 1 0
FANINC5
FANOPV5
FANINC4
FANOPV4
SYSFANIN DIV_B0
SYSFANIN DIV_B1
CPUFANIN0 DIV_B0
CPUFANIN0 DIV_B1
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