LM3S1601 Datasheet, PDF (9/587 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1601 Microcontroller
List of Figures
Figure 1-1. Stellaris LM3S1601 Microcontroller High-Level Block Diagram ............................... 36
Figure 2-1. CPU Block Diagram ............................................................................................. 45
Figure 2-2. TPIU Block Diagram ............................................................................................ 46
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 48
Figure 2-4. Bit-Band Mapping ................................................................................................ 68
Figure 2-5. Data Storage ....................................................................................................... 69
Figure 2-6. Vector Table ........................................................................................................ 75
Figure 2-7. Exception Stack Frame ........................................................................................ 77
Figure 3-1. SRD Use Example ............................................................................................... 91
Figure 4-1. JTAG Module Block Diagram .............................................................................. 150
Figure 4-2. Test Access Port State Machine ......................................................................... 154
Figure 4-3. IDCODE Register Format ................................................................................... 160
Figure 4-4. BYPASS Register Format ................................................................................... 160
Figure 4-5. Boundary Scan Register Format ......................................................................... 161
Figure 5-1. Basic RST Configuration .................................................................................... 164
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 165
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 165
Figure 5-4. Power Architecture ............................................................................................ 167
Figure 5-5. Main Clock Tree ................................................................................................ 170
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 226
Figure 6-2. Clock Source Using Crystal ................................................................................ 228
Figure 6-3. Clock Source Using Dedicated Oscillator ............................................................. 229
Figure 7-1. Flash Block Diagram .......................................................................................... 246
Figure 8-1. GPIO Port Block Diagram ................................................................................... 280
Figure 8-2. GPIODATA Write Example ................................................................................. 281
Figure 8-3. GPIODATA Read Example ................................................................................. 281
Figure 9-1. GPTM Module Block Diagram ............................................................................ 321
Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 326
Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 327
Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 328
Figure 10-1. WDT Module Block Diagram .............................................................................. 358
Figure 11-1. UART Module Block Diagram ............................................................................. 382
Figure 11-2. UART Character Frame ..................................................................................... 384
Figure 11-3. IrDA Data Modulation ......................................................................................... 386
Figure 12-1. SSI Module Block Diagram ................................................................................. 424
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 427
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 428
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 429
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 429
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 430
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 431
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 431
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 432
Figure 12-10. MICROWIRE Frame Format (Single Frame) ........................................................ 433
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 434
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 434
June 19, 2012
9
Texas Instruments-Production Data