LM3S1601 Datasheet, PDF (65/587 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1601 Microcontroller
2.4.4
Table 2-5. Memory Access Behavior (continued)
Address Range
Memory Region
Memory Type Execute
Never
(XN)
0xA000.0000 - 0xDFFF.FFFF External device Device
XN
0xE000.0000- 0xE00F.FFFF Private peripheral Strongly
XN
bus
Ordered
0xE010.0000- 0xFFFF.FFFF Reserved
-
-
Description
This region is for external device memory.
This region includes the NVIC, system
timer, and system control block.
-
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M3 has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 88.
The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch
target addresses.
Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
■ The processor has multiple bus interfaces.
■ Memory or devices in the memory map have different wait states.
■ Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” on page 64 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M3
has the following memory barrier instructions:
■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.
■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
■ MPU programming
– If the MPU settings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.
June 19, 2012
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