LM3S1601 Datasheet, PDF (568/587 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Register Quick Reference
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0
GPIOPUR, type R/W, offset 0x510, reset - (see page 301)
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 (see page 302)
PUE
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 (see page 303)
PDE
SRL
GPIODEN, type R/W, offset 0x51C, reset - (see page 304)
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 (see page 305)
GPIOCR, type -, offset 0x524, reset - (see page 306)
LOCK
LOCK
DEN
CR
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 308)
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 309)
PID4
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 310)
PID5
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 311)
PID6
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 (see page 312)
PID7
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 313)
PID0
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 314)
PID1
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 315)
PID2
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 316)
PID3
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 317)
CID0
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 318)
CID1
CID2
568
June 19, 2012
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