LM3S1601 Datasheet, PDF (16/587 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 205
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 206
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 209
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 212
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 215
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 217
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 219
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 221
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 222
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 224
Hibernation Module ..................................................................................................................... 225
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 234
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 235
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 236
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 237
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 238
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 240
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 241
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 242
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 243
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 244
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 245
Internal Memory ........................................................................................................................... 246
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 252
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 253
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 254
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 256
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 257
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 258
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 260
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 261
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 262
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 263
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 264
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 265
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 266
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 267
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 268
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 269
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 270
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 271
General-Purpose Input/Outputs (GPIOs) ................................................................................... 272
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 286
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 287
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 288
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 289
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 290
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 291
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June 19, 2012
Texas Instruments-Production Data