LM3S1601 Datasheet, PDF (322/587 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

General-Purpose Timers
Table 9-2. General-Purpose Timers Signals (100LQFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
CCP0
66
I/O
TTL
Capture/Compare/PWM 0.
CCP1
100
I/O
TTL
Capture/Compare/PWM 1.
CCP2
67
I/O
TTL
Capture/Compare/PWM 2.
CCP3
23
I/O
TTL
Capture/Compare/PWM 3.
CCP4
22
I/O
TTL
Capture/Compare/PWM 4.
CCP5
25
I/O
TTL
Capture/Compare/PWM 5.
CCP6
86
I/O
TTL
Capture/Compare/PWM 6.
CCP7
85
I/O
TTL
Capture/Compare/PWM 7.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 9-3. General-Purpose Timers Signals (108BGA)
Pin Name
Pin Number Pin Type Buffer Type^a Description
CCP0
E12
I/O
TTL
Capture/Compare/PWM 0.
CCP1
F1
I/O
TTL
Capture/Compare/PWM 1.
CCP2
D12
I/O
TTL
Capture/Compare/PWM 2.
CCP3
M2
I/O
TTL
Capture/Compare/PWM 3.
CCP4
L2
I/O
TTL
Capture/Compare/PWM 4.
CCP5
L1
I/O
TTL
Capture/Compare/PWM 5.
CCP6
C9
I/O
TTL
Capture/Compare/PWM 6.
CCP7
C8
I/O
TTL
Capture/Compare/PWM 7.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
9.3 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 333),
the GPTM TimerA Mode (GPTMTAMR) register (see page 334), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 336). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
9.3.1
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 347) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 348). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 351) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 352).
322
June 19, 2012
Texas Instruments-Production Data