LM3S1601 Datasheet, PDF (552/587 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Electrical Characteristics
Figure 18-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=0)
SSIClk
(SPO=1)
SSITx
(master)
SSIRx
(slave)
S4
S6 S7
MSB
S5
S8 S9
MSB
S1
S2
S3
LSB
LSB
SSIFss
18.2.9
Inter-Integrated Circuit (I²C) Interface
Table 18-18. I²C Characteristics
Parameter
No.
Parameter Parameter Name
Min Nom Max
Unit
I1^a
t_SCH
Start condition hold time
36
-
-
system clocks
I2^a
t_LP
Clock Low period
36
-
-
system clocks
I3^b
t_SRT
I2CSCL/I2CSDA rise time (V_IL =0.5 V
-
- (see note
ns
to V _IH =2.4 V)
b)
I4^a
t_DH
Data hold time
2
-
-
system clocks
I5^c
t_SFT
I2CSCL/I2CSDA fall time (V_IH =2.4 V
-
9
10
ns
to V _IL =0.5 V)
I6^a
t_HT
Clock High time
24
-
-
system clocks
I7^a
t_DS
Data setup time
18
-
-
system clocks
I8^a
t_SCSR
Start condition setup time (for repeated 36
-
-
system clocks
start condition only)
I9^a
t_SCS
Stop condition setup time
24
-
-
system clocks
a. Values depend on the value programmed into the TPR bit in the I²C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I ²C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
552
June 19, 2012
Texas Instruments-Production Data