LM3S1601 Datasheet, PDF (11/587 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1601 Microcontroller
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Revision History .................................................................................................. 20
Documentation Conventions ................................................................................ 26
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 48
Processor Register Map ....................................................................................... 49
PSR Register Combinations ................................................................................. 54
Memory Map ....................................................................................................... 62
Memory Access Behavior ..................................................................................... 64
SRAM Memory Bit-Banding Regions .................................................................... 66
Peripheral Memory Bit-Banding Regions ............................................................... 67
Exception Types .................................................................................................. 72
Interrupts ............................................................................................................ 73
Exception Return Behavior ................................................................................... 78
Faults ................................................................................................................. 79
Fault Status and Fault Address Registers .............................................................. 80
Cortex-M3 Instruction Summary ........................................................................... 82
Core Peripheral Register Regions ......................................................................... 85
Memory Attributes Summary ................................................................................ 88
TEX, S, C, and B Bit Field Encoding ..................................................................... 91
Cache Policy for Memory Attribute Encoding ......................................................... 92
AP Bit Field Encoding .......................................................................................... 92
Memory Region Attributes for Stellaris Microcontrollers .......................................... 92
Peripherals Register Map ..................................................................................... 93
Interrupt Priority Levels ...................................................................................... 118
Example SIZE Field Values ................................................................................ 146
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 150
JTAG_SWD_SWO Signals (108BGA) ................................................................. 151
JTAG Port Pins Reset State ............................................................................... 151
JTAG Instruction Register Commands ................................................................. 158
System Control & Clocks Signals (100LQFP) ...................................................... 162
System Control & Clocks Signals (108BGA) ........................................................ 162
Reset Sources ................................................................................................... 163
Clock Source Options ........................................................................................ 168
Possible System Clock Frequencies Using the SYSDIV Field ............................... 171
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 171
System Control Register Map ............................................................................. 175
RCC2 Fields that Override RCC fields ................................................................. 189
Hibernate Signals (100LQFP) ............................................................................. 226
Hibernate Signals (108BGA) .............................................................................. 227
Hibernation Module Register Map ....................................................................... 233
Flash Protection Policy Combinations ................................................................. 247
User-Programmable Flash Memory Resident Registers ....................................... 250
Flash Register Map ............................................................................................ 250
GPIO Pins With Non-Zero Reset Values .............................................................. 273
GPIO Pins and Alternate Functions (100LQFP) ................................................... 273
GPIO Pins and Alternate Functions (108BGA) ..................................................... 274
GPIO Signals (100LQFP) ................................................................................... 276
June 19, 2012
11
Texas Instruments-Production Data