LM3S1601 Datasheet, PDF (10/587 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
Figure 13-1. I²C Block Diagram ............................................................................................. 463
Figure 13-2. I²C Bus Configuration ........................................................................................ 464
Figure 13-3. START and STOP Conditions ............................................................................. 464
Figure 13-4. Complete Data Transfer with a 7-Bit Address ....................................................... 465
Figure 13-5. R/S Bit in First Byte ............................................................................................ 465
Figure 13-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 465
Figure 13-7. Master Single SEND .......................................................................................... 469
Figure 13-8. Master Single RECEIVE ..................................................................................... 470
Figure 13-9. Master Burst SEND ........................................................................................... 471
Figure 13-10. Master Burst RECEIVE ...................................................................................... 472
Figure 13-11. Master Burst RECEIVE after Burst SEND ............................................................ 473
Figure 13-12. Master Burst SEND after Burst RECEIVE ............................................................ 474
Figure 13-13. Slave Command Sequence ................................................................................ 475
Figure 14-1. Analog Comparator Module Block Diagram ......................................................... 499
Figure 14-2. Structure of Comparator Unit .............................................................................. 501
Figure 14-3. Comparator Internal Reference Structure ............................................................ 501
Figure 15-1. 100-Pin LQFP Package Pin Diagram .................................................................. 511
Figure 15-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 512
Figure 18-1. Load Conditions ................................................................................................ 544
Figure 18-2. JTAG Test Clock Input Timing ............................................................................. 547
Figure 18-3. JTAG Test Access Port (TAP) Timing .................................................................. 547
Figure 18-4. JTAG TRST Timing ............................................................................................ 547
Figure 18-5. External Reset Timing (RST) .............................................................................. 548
Figure 18-6. Power-On Reset Timing ..................................................................................... 548
Figure 18-7. Brown-Out Reset Timing .................................................................................... 548
Figure 18-8. Software Reset Timing ....................................................................................... 549
Figure 18-9. Watchdog Reset Timing ..................................................................................... 549
Figure 18-10. Hibernation Module Timing ................................................................................. 550
Figure 18-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 551
Figure 18-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 551
Figure 18-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 552
Figure 18-14. I²C Timing ......................................................................................................... 553
Figure D-1. Stellaris LM3S1601 100-Pin LQFP Package Dimensions ..................................... 579
Figure D-2. 100-Pin LQFP Tray Dimensions .......................................................................... 581
Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 582
Figure D-4. Stellaris LM3S1601 108-Ball BGA Package Dimensions ...................................... 583
Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 585
Figure D-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 586
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June 19, 2012
Texas Instruments-Production Data